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| REJ09B0283-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series H8S/2676 H8S/2675 H8S/2674R H8S/2673 H8S/2670 HD64F2676 HD6432676 HD6432675 HD6412674R HD6432673 HD6412670 Rev. 3.00 Revision Date: Mar 17, 2006 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00 Mar 17, 2006 page ii of l General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00 Mar 17, 2006 page iii of l Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions in This Edition 5. Contents 6. Overview 7. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. List of Registers 9. Electrical Characteristics 10. Appendix The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 3.00 Mar 17, 2006 page iv of l Preface The H8S/2678 Group and H8S/2678R Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas' original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space. This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O ports as on-chip peripheral modules required for system configuration A high functionality bus controller is also provided, enabling fast and easy connection of DRAM, SDRAM, and other kinds of memory. A single-power flash memory (F-ZTAT*) version and masked ROM version are available for this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. This manual describes this LSI's hardware. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. Rev. 3.00 Mar 17, 2006 page v of l In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 23, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com H8S/2678 Group and H8S/2678R Group manuals: Document Title H8S/2678 Group, H8S/2678R Group Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139 User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual Document No. REJ10B0058 ADE-702-037 ADE-702-231 ADE-702-201 Rev. 3.00 Mar 17, 2006 page vi of l Main Revisions in This Edition Item All Page -- Revision (See Manual for Details) All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from "series" to "group" Symbols amended Upper column address strobe/upper data mask enable (Before) UCAS/DQMU (After) UCAS/DQMU Lower column address strobe/upper data mask enable (Before) LCAS/DQML (After) LCAS/DQML 124 I/O description amended Data Transfer acknowledge 0 (DMAC) (Before) DACK0 (After) Output 7.5.1 Transfer Modes Table 7.4 DMAC Transfer Modes 288 Table 7.4 amended Transfer Mode Short address mode Dual address mode (1) Sequential mode * Memory address incremented or decremented by 1 or 2 * Number of transfers: 1 to 65,536 (2) Idle mode * Memory address fixed * Number of transfers: 1 to 65,536 (3) Repeat mode * Memory address incremented or decremented by 1 or 2 * Continues transfer after sending number of transfers (1 to 256) and restoring the initial value Transfer Source * TPU channel 0 to 5 compare match/input capture A interrupt * SCI transmission complete interrupt * SCI reception complete interrupt * A/D converter conversion end interrupt * External request Remarks * Up to 4 channels can operate independently * External request applies to channel B only * Single address mode applies to channel B only 6.2 Input/Output Pins Table 6.1 Pin Configuration 124 289 Transfer Mode Full address mode Normal mode (1) Auto-request * Transfer request is internally held * Number of transfers (1 to 65,536) is continuously sent * Burst/cycle steal transfer can be selected Transfer Source Auto-request Remarks * Max. 2-channel operation, combining channels A and B Section 10 I/O Ports Table 10.1 Port Functions 428 to 432 Notes amended 1 Modes 3* , 7 CKE* 2 WE* 2 DQML* 2 DQMU* 2 2 2 2 CAS* RAS* SDRAM* 432 Notes: 1. Mode 3 is not supported in H8S/2378 Group. 2. These pins are not supported in H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page vii of l Item 10.2.4 Pin Functions Page 445 Revision (See Manual for Details) * P27/PO7/TIOCB5/(IRQ15)/EDRAK1 Description amended (Before) IRQ5 interrupt input (After) IRQ15 interrupt input 445 10.6.4 Pin Functions 471 Note 2 amended Note: 2. IRQ15 input when ITS15 = 1. * P61/TMRI1/DREQ1/IRQ9 Description amended The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit P61DDR, and bit ITS9 in ITSR. 471 * P60/TMRI0/DREQ0/IRQ8 Description amended The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit P60DDR, and bit ITS8 in ITSR. 10.7.4 Pin Functions 477 * P71/DREQ1/EDREQ1 Description amended The pin function is switched as shown below according to the combination of bit P71DDR and bit DMACS in PFCR2. 477 * P70/DREQ0/EDREQ0 Description amended The pin function is switched as shown below according to the combination of bit P70DDR and bit DMACS in PFCR2. 10.9.5 Port A Open Drain Control Register (PAODR) 10.9.6 Port Function Control Register 1 (PFCR1) 486 Note deleted from bit table 486 Note * added Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page viii of l Item 10.15.4 Pin Functions Page 515 Revision (See Manual for Details) * PG3/CS3/RAS3/CAS, PG2/CS2/RAS2/RAS Description amended The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits RMTS2 to RMTS0. 515 * PG1/CS1, PG0/CS0 Description amended The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, and bit CSnE. 10.16.4 Pin Functions 520 * PH1/CS5/RAS5/SDRAM Description amended The pin function is switched as shown below according to the operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR. 11.1 Features Table 11.1 TPU Functions 523 Table 11.1 amended Item Channel 0 Channel 1 TGR compare match or input capture TGRA_1 compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture Channel 2 TGR compare match or input capture TGRA_2 compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture Channel 3 TGR compare match or input capture TGRA_3 compare match or input capture TGRA_3 compare match or input capture Channel 4 TGR compare match or input capture TGRA_4 compare match or input capture TGRA_4 compare match or input capture Channel 5 TGR compare match or input capture TGRA_5 compare match or input capture TGRA_5 compare match or input capture -- DTC TGR activation compare match or input capture DMAC TGRA_0 activation compare match or input capture A/D TGRA_0 converter compare trigger match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_3/ -- TGRB_3 compare match or input capture 11.3.9 Timer Synchronous Register (TSYR) 15.3.9 Bit Rate Generator (BRR) Table 15.2 Relationships between N Setting in BRR and Bit Rate B 558 Bits 7, 6 initial value amended (Before) - (After) All 0 679 Table 15.2 amended Mode Smart Card Interface Mode Bit Rate B= Error x 106 Error (%) = S x 22n+1 x (N + 1) { B x S x 2 x 10x (N + 1) - 1} x 100 6 2n+1 Rev. 3.00 Mar 17, 2006 page ix of l Item 17.4 Operation Page 769 Revision (See Manual for Details) Description added [2] Set the DAOE0 bit ... The output value is expressed by the following formula: DADR contents x Vref 256 19.12 Usage Notes Figure 19.12 PowerOn/Off Timing (H8S/2678Group) tOSC1 VCC Min 0 s 804 Figure 19.12 amended Wait time: x Programming/ erasing Wait time: 100 s possible FWE tMDS*3 Min 0 s MD2 to MD0*1 tMDS*3 RES SWE set SWE bit (1) Boot Mode Programming/ erasing possible Wait time: 100 s SWE cleared Wait time: x tOSC1 VCC Min 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit (2) User Program Mode SWE cleared Section 20 Masked ROM 810 Description amended The operating mode enables or disables the on-chip ROM. The operating mode is selected by the mode setting pins, such as the FWE and MD2 to MD0 pins shown in table 3.1. ... Rev. 3.00 Mar 17, 2006 page x of l Item 21.2.1 Connecting a Crystal Resonator 21.2.2 External Clock Input 24.6 Flash Memory Characteristics Table 24.13 Flash Memory Characteristics Page 814 Revision (See Manual for Details) Description amended ... shown in table 21.2. When a crystal resonator is used, the range of its frequencies is from 8 to 25 MHz. 815 Description amended ... for the external clock. When an external clock is used, the range of its frequencies is from 8 to 25 MHz. 907, 908 Table 24.13 amended and notes *7, *8, *9 added Item Programming time*1 *2 *4 Erase time*1 *3 *6 Reprogramming count Data retention time*9 Programming Wait time after SWE bit setting*1 Symbol Min tP tE NWEC tDRP x -- -- Typ 10 50 Max 200 1000 Unit ms/ 128 bytes ms/ 128 bytes Times Years s Test Conditions 100*7 10,000*8 -- 10 1 -- -- -- -- Notes: 7. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 8. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 9. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. C. Package Dimensions Figure C.1 Package Dimensions (FP-144H) Figure C.2 Package Dimensions (FP-144G) 920 Figure C.2 replaced 919 Figure C.1 replaced Rev. 3.00 Mar 17, 2006 page xi of l Rev. 3.00 Mar 17, 2006 page xii of l Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Features ............................................................................................................................. Block Diagram .................................................................................................................. Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 1.3.3 Pin Functions ....................................................................................................... 1 1 3 5 5 7 13 Section 2 CPU ...................................................................................................................... 21 2.1 Features ............................................................................................................................. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.2 Differences from H8/300 CPU ............................................................................ 2.1.3 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... 2.2.1 Normal Mode....................................................................................................... 2.2.2 Advanced Mode................................................................................................... Address Space................................................................................................................... Registers............................................................................................................................ 2.4.1 General Registers ................................................................................................. 2.4.2 Program Counter (PC) ......................................................................................... 2.4.3 Extended Register (EXR) .................................................................................... 2.4.4 Condition-Code Register (CCR) .......................................................................... 2.4.5 Multiply-Accumulate Register (MAC) ................................................................ 2.4.6 Initial Values of CPU Internal Registers.............................................................. Data Formats..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Table of Instructions Classified by Function ....................................................... 2.6.2 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Register Direct--Rn............................................................................................. 2.7.2 Register Indirect--@ERn .................................................................................... 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn).............. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn .. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32.................................... 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 ................................................................. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC).................................... 21 22 22 23 24 24 26 28 29 30 31 31 32 33 33 34 34 36 37 38 47 48 49 49 49 50 50 51 51 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 3.00 Mar 17, 2006 page xiii of l 2.8 2.9 2.7.8 Memory Indirect--@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. Processing States............................................................................................................... Usage Note........................................................................................................................ 2.9.1 Usage Notes on Bit-wise Operation Instructions ................................................. 51 53 55 56 56 Section 3 MCU Operating Modes .................................................................................. 57 3.1 3.2 Operating Mode Selection ................................................................................................ Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 1 ................................................................................................................. 3.3.2 Mode 2 ................................................................................................................. 3.3.3 Mode 3 ................................................................................................................. 3.3.4 Mode 4 ................................................................................................................. 3.3.5 Mode 5 ................................................................................................................. 3.3.6 Mode 6 ................................................................................................................. 3.3.7 Mode 7 ................................................................................................................. 3.3.8 Mode 10 ............................................................................................................... 3.3.9 Mode 11 ............................................................................................................... 3.3.10 Mode 12 ............................................................................................................... 3.3.11 Mode 13 ............................................................................................................... 3.3.12 Mode 14 ............................................................................................................... 3.3.13 Mode 15 ............................................................................................................... 3.3.14 Pin Functions ....................................................................................................... Memory Map in Each Operating Mode ............................................................................ 57 58 59 59 61 61 61 61 61 62 62 62 63 63 63 63 63 63 63 65 3.3 3.4 Section 4 Exception Handling ......................................................................................... 75 4.1 4.2 4.3 Exception Handling Types and Priority ............................................................................ Exception Sources and Exception Vector Table ............................................................... Reset.................................................................................................................................. 4.3.1 Reset exception handling ..................................................................................... 4.3.2 Interrupts after Reset............................................................................................ 4.3.3 On-Chip Peripheral Functions after Reset Release .............................................. Traces................................................................................................................................ Interrupts ........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Usage Note........................................................................................................................ 75 75 77 77 79 79 80 80 81 82 83 4.4 4.5 4.6 4.7 4.8 Rev. 3.00 Mar 17, 2006 page xiv of l Section 5 Interrupt Controller .......................................................................................... 85 5.1 5.2 5.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 5.3.1 Interrupt Control Register (INTCR)..................................................................... 5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 5.3.3 IRQ Enable Register (IER) .................................................................................. 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.3.5 IRQ Status Register (ISR).................................................................................... 5.3.6 IRQ Pin Select Register (ITSR) ........................................................................... 5.3.7 Software Standby Release IRQ Enable Register (SSIER) ................................... Interrupt Sources............................................................................................................... 5.4.1 External Interrupts ............................................................................................... 5.4.2 Internal Interrupts................................................................................................. Interrupt Exception Handling Vector Table...................................................................... Interrupt Control Modes and Interrupt Operation ............................................................. 5.6.1 Interrupt Control Mode 0 ..................................................................................... 5.6.2 Interrupt Control Mode 2 ..................................................................................... 5.6.3 Interrupt Exception Handling Sequence .............................................................. 5.6.4 Interrupt Response Times .................................................................................... 5.6.5 DTC and DMAC Activation by Interrupt ............................................................ Usage Notes ...................................................................................................................... 5.7.1 Contention between Interrupt Generation and Disabling..................................... 5.7.2 Instructions that Disable Interrupts ...................................................................... 5.7.3 Times when Interrupts are Disabled .................................................................... 5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 5.7.6 Note on IRQ Status Register (ISR) ...................................................................... 85 87 87 88 88 91 92 98 98 100 101 101 102 102 107 108 110 112 114 115 117 117 118 118 119 119 119 5.4 5.5 5.6 5.7 Section 6 Bus Controller (BSC) ...................................................................................... 121 6.1 6.2 6.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 6.3.1 Bus Width Control Register (ABWCR)............................................................... 6.3.2 Access State Control Register (ASTCR) ............................................................. 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 121 123 125 126 126 127 132 133 135 Rev. 3.00 Mar 17, 2006 page xv of l 6.4 6.5 6.6 6.7 6.3.7 Bus Control Register (BCR) ................................................................................ 6.3.8 DRAM Control Register (DRAMCR) ................................................................. 6.3.9 DRAM Access Control Register (DRACCR) ...................................................... 6.3.10 Refresh Control Register (REFCR) ..................................................................... 6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... Bus Control ....................................................................................................................... 6.4.1 Area Division ....................................................................................................... 6.4.2 Bus Specifications................................................................................................ 6.4.3 Memory Interfaces ............................................................................................... 6.4.4 Chip Select Signals .............................................................................................. Basic Bus Interface ........................................................................................................... 6.5.1 Data Size and Data Alignment............................................................................. 6.5.2 Valid Strobes........................................................................................................ 6.5.3 Basic Operation Timing ....................................................................................... 6.5.4 Wait Control ........................................................................................................ 6.5.5 Read Strobe (RD) Timing .................................................................................... 6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. DRAM Interface ............................................................................................................... 6.6.1 Setting DRAM Space........................................................................................... 6.6.2 Address Multiplexing........................................................................................... 6.6.3 Data Bus............................................................................................................... 6.6.4 Pins Used for DRAM Interface............................................................................ 6.6.5 Basic Timing........................................................................................................ 6.6.6 Column Address Output Cycle Control ............................................................... 6.6.7 Row Address Output State Control...................................................................... 6.6.8 Precharge State Control ....................................................................................... 6.6.9 Wait Control ........................................................................................................ 6.6.10 Byte Access Control ............................................................................................ 6.6.11 Burst Operation.................................................................................................... 6.6.12 Refresh Control.................................................................................................... 6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.... Synchronous DRAM Interface.......................................................................................... 6.7.1 Setting Continuous Synchronous DRAM Space.................................................. 6.7.2 Address Multiplexing........................................................................................... 6.7.3 Data Bus............................................................................................................... 6.7.4 Pins Used for Synchronous DRAM Interface ...................................................... 6.7.5 Synchronous DRAM Clock ................................................................................. 6.7.6 Basic Operation Timing ....................................................................................... 6.7.7 CAS Latency Control........................................................................................... 6.7.8 Row Address Output State Control...................................................................... 136 138 144 149 152 152 152 152 154 156 157 158 158 160 160 169 170 171 173 173 173 174 175 176 177 178 180 181 184 185 190 195 198 198 199 200 200 202 202 204 206 Rev. 3.00 Mar 17, 2006 page xvi of l 6.8 6.9 6.10 6.11 6.12 6.13 6.14 Precharge State Count.......................................................................................... Bus Cycle Control in Write Cycle ....................................................................... Byte Access Control ............................................................................................ Burst Operation.................................................................................................... Refresh Control.................................................................................................... Mode Register Setting of Synchronous DRAM................................................... DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface .................................................................................................. Burst ROM Interface......................................................................................................... 6.8.1 Basic Timing........................................................................................................ 6.8.2 Wait Control ........................................................................................................ 6.8.3 Write Access ........................................................................................................ Idle Cycle .......................................................................................................................... 6.9.1 Operation ............................................................................................................. 6.9.2 Pin States in Idle Cycle ........................................................................................ Write Data Buffer Function .............................................................................................. Bus Release....................................................................................................................... 6.11.1 Operation ............................................................................................................. 6.11.2 Pin States in External Bus Released State............................................................ 6.11.3 Transition Timing ................................................................................................ Bus Arbitration.................................................................................................................. 6.12.1 Operation ............................................................................................................. 6.12.2 Bus Transfer Timing ............................................................................................ Bus Controller Operation in Reset .................................................................................... Usage Notes ...................................................................................................................... 6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 6.14.2 External Bus Release Function and Software Standby ........................................ 6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing............... 6.14.4 BREQO Output Timing ....................................................................................... 6.14.5 Notes on Usage of the Synchronous DRAM ....................................................... 6.7.9 6.7.10 6.7.11 6.7.12 6.7.13 6.7.14 6.7.15 208 210 211 214 217 223 224 229 229 231 231 232 232 249 249 250 251 252 253 255 255 255 257 257 257 257 258 258 258 Section 7 DMA Controller (DMAC) ............................................................................. 259 7.1 7.2 7.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 7.3.1 Memory Address Registers (MARA and MARB) ............................................... 7.3.2 I/O Address Registers (IOARA and IOARB) ...................................................... 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 7.3.4 DMA Control Registers (DMACRA and DMACRB) ......................................... 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 7.3.6 DMA Write Enable Register (DMAWER) .......................................................... 259 261 261 263 263 264 265 272 283 Rev. 3.00 Mar 17, 2006 page xvii of l 7.4 7.5 7.6 7.7 7.3.7 DMA Terminal Control Register (DMATCR)..................................................... Activation Sources ............................................................................................................ 7.4.1 Activation by Internal Interrupt Request.............................................................. 7.4.2 Activation by External Request ........................................................................... 7.4.3 Activation by Auto-Request................................................................................. Operation .......................................................................................................................... 7.5.1 Transfer Modes .................................................................................................... 7.5.2 Sequential Mode .................................................................................................. 7.5.3 Idle Mode............................................................................................................. 7.5.4 Repeat Mode ........................................................................................................ 7.5.5 Single Address Mode........................................................................................... 7.5.6 Normal Mode....................................................................................................... 7.5.7 Block Transfer Mode ........................................................................................... 7.5.8 Basic Bus Cycles.................................................................................................. 7.5.9 DMA Bus Cycles (Dual Address Mode) ............................................................. 7.5.10 DMA Bus Cycles (Single Address Mode) ........................................................... 7.5.11 Write Data Buffer Function ................................................................................. 7.5.12 Multi-Channel Operation ..................................................................................... 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC ..................................................................................................... 7.5.14 DMAC and NMI Interrupts.................................................................................. 7.5.15 Forced Termination of DMAC Operation............................................................ 7.5.16 Clearing Full Address Mode ................................................................................ Interrupt Sources............................................................................................................... Usage Notes ...................................................................................................................... 7.7.1 DMAC Register Access during Operation........................................................... 7.7.2 Module Stop......................................................................................................... 7.7.3 Write Data Buffer Function ................................................................................. 7.7.4 TEND Output....................................................................................................... 7.7.5 Activation by Falling Edge on DREQ Pin ........................................................... 7.7.6 Activation Source Acceptance ............................................................................. 7.7.7 Internal Interrupt after End of Transfer................................................................ 7.7.8 Channel Re-Setting .............................................................................................. 285 286 287 287 288 288 288 290 292 295 298 301 304 309 310 318 324 325 326 327 327 328 329 330 330 331 331 332 333 334 334 334 Section 8 EXDMA Controller ......................................................................................... 335 8.1 8.2 8.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 8.3.1 EXDMA Source Address Register (EDSAR) ...................................................... 8.3.2 EXDMA Destination Address Register (EDDAR) .............................................. 8.3.3 EXDMA Transfer Count Register (EDTCR)....................................................... 335 337 338 338 339 339 Rev. 3.00 Mar 17, 2006 page xviii of l 8.4 8.5 8.6 8.3.4 EXDMA Mode Control Register (EDMDR) ....................................................... 8.3.5 EXDMA Address Control Register (EDACR) .................................................... Operation .......................................................................................................................... 8.4.1 Transfer Modes .................................................................................................... 8.4.2 Address Modes .................................................................................................... 8.4.3 DMA Transfer Requests ...................................................................................... 8.4.4 Bus Modes ........................................................................................................... 8.4.5 Transfer Modes .................................................................................................... 8.4.6 Repeat Area Function .......................................................................................... 8.4.7 Registers during DMA Transfer Operation.......................................................... 8.4.8 Channel Priority Order......................................................................................... 8.4.9 EXDMAC Bus Cycles (Dual Address Mode)...................................................... 8.4.10 EXDMAC Bus Cycles (Single Address Mode) ................................................... 8.4.11 Examples of Operation Timing in Each Mode .................................................... 8.4.12 Ending DMA Transfer ......................................................................................... 8.4.13 Relationship between EXDMAC and Other Bus Masters ................................... Interrupt Sources............................................................................................................... Usage Notes ...................................................................................................................... 8.6.1 EXDMAC Register Access during Operation ..................................................... 8.6.2 Module Stop State................................................................................................ 8.6.3 EDREQ Pin Falling Edge Activation................................................................... 8.6.4 Activation Source Acceptance ............................................................................. 8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR ...................................... 8.6.6 ETEND Pin and CBR Refresh Cycle................................................................... 341 346 350 350 351 355 355 357 359 361 366 369 376 380 393 394 395 398 398 398 398 399 399 399 Section 9 Data Transfer Controller (DTC)................................................................... 401 9.1 9.2 Features ............................................................................................................................. Register Descriptions ........................................................................................................ 9.2.1 DTC Mode Register A (MRA) ............................................................................ 9.2.2 DTC Mode Register B (MRB)............................................................................. 9.2.3 DTC Source Address Register (SAR).................................................................. 9.2.4 DTC Destination Address Register (DAR).......................................................... 9.2.5 DTC Transfer Count Register A (CRA) .............................................................. 9.2.6 DTC Transfer Count Register B (CRB)............................................................... 9.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 9.2.8 DTC Vector Register (DTVECR)........................................................................ Activation Sources ............................................................................................................ Location of Register Information and DTC Vector Table ................................................ Operation .......................................................................................................................... 9.5.1 Normal Mode....................................................................................................... 9.5.2 Repeat Mode ........................................................................................................ 401 402 403 404 405 405 405 405 405 406 407 408 410 412 413 9.3 9.4 9.5 Rev. 3.00 Mar 17, 2006 page xix of l 9.6 9.7 9.8 9.5.3 Block Transfer Mode ........................................................................................... 9.5.4 Chain Transfer ..................................................................................................... 9.5.5 Interrupt Sources.................................................................................................. 9.5.6 Operation Timing................................................................................................. 9.5.7 Number of DTC Execution States........................................................................ Procedures for Using DTC................................................................................................ 9.6.1 Activation by Interrupt......................................................................................... 9.6.2 Activation by Software ........................................................................................ Examples of Use of the DTC ............................................................................................ 9.7.1 Normal Mode....................................................................................................... 9.7.2 Chain Transfer ..................................................................................................... 9.7.3 Chain Transfer when Counter = 0........................................................................ 9.7.4 Software Activation ............................................................................................. Usage Notes ...................................................................................................................... 9.8.1 Module Stop Mode Setting .................................................................................. 9.8.2 On-Chip RAM ..................................................................................................... 9.8.3 DTCE Bit Setting................................................................................................. 414 415 416 417 418 420 420 420 421 421 422 423 425 426 426 426 426 Section 10 I/O Ports............................................................................................................ 427 10.1 Port 1................................................................................................................................. 10.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 10.1.2 Port 1 Data Register (P1DR)................................................................................ 10.1.3 Port 1 Register (PORT1)...................................................................................... 10.1.4 Pin Functions ....................................................................................................... 10.2 Port 2................................................................................................................................. 10.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 10.2.2 Port 2 Data Register (P2DR)................................................................................ 10.2.3 Port 2 Register (PORT2)...................................................................................... 10.2.4 Pin Functions ....................................................................................................... 10.3 Port 3................................................................................................................................. 10.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 10.3.2 Port 3 Data Register (P3DR)................................................................................ 10.3.3 Port 3 Register (PORT3)...................................................................................... 10.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 10.3.5 Port Function Control Register 2 (PFCR2) .......................................................... 10.3.6 Pin Functions ....................................................................................................... 10.4 Port 4................................................................................................................................. 10.4.1 Port 4 Register (PORT4)...................................................................................... 10.4.2 Pin Functions ....................................................................................................... 10.5 Port 5................................................................................................................................. 10.5.1 Port 5 Data Direction Register (P5DDR)............................................................. Rev. 3.00 Mar 17, 2006 page xx of l 432 432 433 433 434 443 443 444 444 445 454 454 455 455 456 457 458 461 461 461 462 463 10.6 10.7 10.8 10.9 10.10 10.11 10.5.2 Port 5 Data Register (P5DR)................................................................................ 10.5.3 Port 5 Register (PORT5)...................................................................................... 10.5.4 Pin Functions ....................................................................................................... Port 6................................................................................................................................. 10.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 10.6.2 Port 6 Data Register (P6DR)................................................................................ 10.6.3 Port 6 Register (PORT6)...................................................................................... 10.6.4 Pin Functions ....................................................................................................... Port 7................................................................................................................................. 10.7.1 Port 7 Data Direction Register (P7DDR)............................................................. 10.7.2 Port 7 Data Register (P7DR)................................................................................ 10.7.3 Port 7 Register (PORT7)...................................................................................... 10.7.4 Pin Functions ....................................................................................................... Port 8................................................................................................................................. 10.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 10.8.2 Port 8 Data Register (P8DR)................................................................................ 10.8.3 Port 8 Register (PORT8)...................................................................................... 10.8.4 Pin Functions ....................................................................................................... Port A................................................................................................................................ 10.9.1 Port A Data Direction Register (PADDR) ........................................................... 10.9.2 Port A Data Register (PADR) .............................................................................. 10.9.3 Port A Register (PORTA) .................................................................................... 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................ 10.9.5 Port A Open Drain Control Register (PAODR)................................................... 10.9.6 Port Function Control Register 1 (PFCR1) .......................................................... 10.9.7 Pin Functions ....................................................................................................... 10.9.8 Port A Input Pull-Up MOS States........................................................................ Port B ................................................................................................................................ 10.10.1 Port B Data Direction Register (PBDDR)............................................................ 10.10.2 Port B Data Register (PBDR) .............................................................................. 10.10.3 Port B Register (PORTB) .................................................................................... 10.10.4 Port B Pull-Up MOS Control Register (PBPCR)................................................. 10.10.5 Pin Functions ....................................................................................................... 10.10.6 Port B Input Pull-Up MOS States ........................................................................ Port C ................................................................................................................................ 10.11.1 Port C Data Direction Register (PCDDR)............................................................ 10.11.2 Port C Data Register (PCDR) .............................................................................. 10.11.3 Port C Register (PORTC) .................................................................................... 10.11.4 Port C Pull-Up MOS Control Register (PCPCR)................................................. 10.11.5 Pin Functions ....................................................................................................... 10.11.6 Port C Input Pull-Up MOS States ........................................................................ 463 464 464 467 467 468 468 469 472 472 473 473 474 478 478 479 479 480 483 484 485 485 486 486 486 488 489 489 490 490 491 491 492 492 493 493 494 494 495 495 496 Rev. 3.00 Mar 17, 2006 page xxi of l 10.12 Port D................................................................................................................................ 10.12.1 Port D Data Direction Register (PDDDR) ........................................................... 10.12.2 Port D Data Register (PDDR) .............................................................................. 10.12.3 Port D Register (PORTD) .................................................................................... 10.12.4 Port D Pull-up Control Register (PDPCR)........................................................... 10.12.5 Pin Functions ....................................................................................................... 10.12.6 Port D Input Pull-Up MOS States........................................................................ 10.13 Port E ................................................................................................................................ 10.13.1 Port E Data Direction Register (PEDDR) ............................................................ 10.13.2 Port E Data Register (PEDR)............................................................................... 10.13.3 Port E Register (PORTE)..................................................................................... 10.13.4 Port E Pull-up Control Register (PEPCR)............................................................ 10.13.5 Pin Functions ....................................................................................................... 10.13.6 Port E Input Pull-Up MOS States ........................................................................ 10.14 Port F................................................................................................................................. 10.14.1 Port F Data Direction Register (PFDDR) ............................................................ 10.14.2 Port F Data Register (PFDR) ............................................................................... 10.14.3 Port F Register (PORTF) ..................................................................................... 10.14.4 Pin Functions ....................................................................................................... 10.15 Port G................................................................................................................................ 10.15.1 Port G Data Direction Register (PGDDR) ........................................................... 10.15.2 Port G Data Register (PGDR) .............................................................................. 10.15.3 Port G Register (PORTG) .................................................................................... 10.15.4 Port Function Control Register 0 (PFCR0) .......................................................... 10.15.5 Pin Functions ....................................................................................................... 10.16 Port H................................................................................................................................ 10.16.1 Port H Data Direction Register (PHDDR) ........................................................... 10.16.2 Port H Data Register (PHDR) .............................................................................. 10.16.3 Port H Register (PORTH) .................................................................................... 10.16.4 Pin Functions ....................................................................................................... 496 497 497 498 498 499 499 500 500 501 501 502 502 503 503 504 505 506 506 510 510 512 512 513 513 516 517 518 518 519 Section 11 16-Bit Timer Pulse Unit (TPU).................................................................. 521 11.1 Features ............................................................................................................................. 11.2 Input/Output Pins .............................................................................................................. 11.3 Register Descriptions ........................................................................................................ 11.3.1 Timer Control Register (TCR) ............................................................................. 11.3.2 Timer Mode Register (TMDR) ............................................................................ 11.3.3 Timer I/O Control Register (TIOR) ..................................................................... 11.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 11.3.5 Timer Status Register (TSR)................................................................................ 11.3.6 Timer Counter (TCNT)........................................................................................ Rev. 3.00 Mar 17, 2006 page xxii of l 521 525 526 528 533 534 552 554 557 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.3.7 Timer General Register (TGR) ............................................................................ 11.3.8 Timer Start Register (TSTR)................................................................................ 11.3.9 Timer Synchronous Register (TSYR) .................................................................. Operation .......................................................................................................................... 11.4.1 Basic Functions.................................................................................................... 11.4.2 Synchronous Operation........................................................................................ 11.4.3 Buffer Operation .................................................................................................. 11.4.4 Cascaded Operation ............................................................................................. 11.4.5 PWM Modes ........................................................................................................ 11.4.6 Phase Counting Mode .......................................................................................... Interrupt Sources............................................................................................................... DTC Activation................................................................................................................. DMAC Activation............................................................................................................. A/D Converter Activation ................................................................................................. Operation Timing.............................................................................................................. 11.9.1 Input/Output Timing ............................................................................................ 11.9.2 Interrupt Signal Timing........................................................................................ Usage Notes ...................................................................................................................... 11.10.1 Module Stop Mode Setting .............................................................................. 11.10.2 Input Clock Restrictions................................................................................... 11.10.3 Caution on Cycle Setting ................................................................................. 11.10.4 Contention between TCNT Write and Clear Operations ................................. 11.10.5 Contention between TCNT Write and Increment Operations.......................... 11.10.6 Contention between TGR Write and Compare Match ..................................... 11.10.7 Contention between Buffer Register Write and Compare Match .................... 11.10.8 Contention between TGR Read and Input Capture.......................................... 11.10.9 Contention between TGR Write and Input Capture......................................... 11.10.10 Contention between Buffer Register Write and Input Capture ........................ 11.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 11.10.12 Contention between TCNT Write and Overflow/Underflow........................... 11.10.13 Multiplexing of I/O Pins .................................................................................. 11.10.14 Interrupts and Module Stop Mode ................................................................... 557 557 558 559 559 564 566 570 572 577 583 585 585 585 586 586 590 594 594 594 595 595 596 597 598 599 600 601 602 603 603 603 Section 12 Programmable Pulse Generator (PPG) .................................................... 605 12.1 Features ............................................................................................................................. 12.2 Input/Output Pins .............................................................................................................. 12.3 Register Descriptions ........................................................................................................ 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 12.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 12.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 12.3.4 PPG Output Control Register (PCR).................................................................... 605 607 607 608 609 610 612 Rev. 3.00 Mar 17, 2006 page xxiii of l 12.3.5 PPG Output Mode Register (PMR)...................................................................... 12.4 Operation .......................................................................................................................... 12.4.1 Output Timing...................................................................................................... 12.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 12.4.4 Non-Overlapping Pulse Output............................................................................ 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output .............................. 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output).................. 12.4.7 Inverted Pulse Output .......................................................................................... 12.4.8 Pulse Output Triggered by Input Capture ............................................................ 12.5 Usage Notes ...................................................................................................................... 12.5.1 Module Stop Mode Setting .................................................................................. 12.5.2 Operation of Pulse Output Pins............................................................................ 613 615 616 617 618 619 621 622 624 625 625 625 625 Section 13 8-Bit Timers (TMR) ...................................................................................... 627 13.1 Features ............................................................................................................................. 13.2 Input/Output Pins .............................................................................................................. 13.3 Register Descriptions ........................................................................................................ 13.3.1 Timer Counter (TCNT)........................................................................................ 13.3.2 Time Constant Register A (TCORA)................................................................... 13.3.3 Time Constant Register B (TCORB) ................................................................... 13.3.4 Timer Control Register (TCR) ............................................................................. 13.3.5 Timer Control/Status Register (TCSR) ................................................................ 13.4 Operation .......................................................................................................................... 13.4.1 Pulse Output......................................................................................................... 13.5 Operation Timing.............................................................................................................. 13.5.1 TCNT Incrementation Timing ............................................................................. 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs ................. 13.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 13.5.4 Timing of Compare Match Clear ......................................................................... 13.5.5 Timing of TCNT External Reset.......................................................................... 13.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 13.6 Operation with Cascaded Connection ............................................................................... 13.6.1 16-Bit Counter Mode ........................................................................................... 13.6.2 Compare Match Count Mode............................................................................... 13.7 Interrupts ........................................................................................................................... 13.7.1 Interrupt Sources and DTC Activation ................................................................ 13.7.2 A/D Converter Activation.................................................................................... 13.8 Usage Notes ...................................................................................................................... 13.8.1 Contention between TCNT Write and Clear........................................................ Rev. 3.00 Mar 17, 2006 page xxiv of l 627 629 629 630 630 630 631 633 636 636 637 637 638 639 639 640 640 641 641 641 642 642 642 643 643 13.8.2 13.8.3 13.8.4 13.8.5 13.8.6 13.8.7 Contention between TCNT Write and Increment ................................................ Contention between TCOR Write and Compare Match ...................................... Contention between Compare Matches A and B ................................................. Switching of Internal Clocks and TCNT Operation............................................. Mode Setting with Cascaded Connection ............................................................ Interrupts in Module Stop Mode.......................................................................... 644 645 646 646 648 648 Section 14 Watchdog Timer............................................................................................. 649 14.1 Features ............................................................................................................................. 14.2 Input/Output Pin................................................................................................................ 14.3 Register Descriptions ........................................................................................................ 14.3.1 Timer Counter (TCNT)........................................................................................ 14.3.2 Timer Control/Status Register (TCSR) ................................................................ 14.3.3 Reset Control/Status Register (RSTCSR) ............................................................ 14.4 Operation .......................................................................................................................... 14.4.1 Watchdog Timer Mode ........................................................................................ 14.4.2 Interval Timer Mode ............................................................................................ 14.5 Interrupt Source ................................................................................................................ 14.6 Usage Notes ...................................................................................................................... 14.6.1 Notes on Register Access..................................................................................... 14.6.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 14.6.3 Changing Value of CKS2 to CKS0...................................................................... 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 14.6.5 Internal Reset in Watchdog Timer Mode............................................................. 14.6.6 System Reset by WDTOVF Signal...................................................................... 649 650 650 651 651 653 654 654 655 656 656 656 658 658 658 659 659 661 661 664 664 665 665 666 666 666 670 673 678 679 688 689 Section 15 Serial Communication Interface (SCI, IrDA) ........................................ 15.1 Features ............................................................................................................................. 15.2 Input/Output Pins .............................................................................................................. 15.3 Register Descriptions ........................................................................................................ 15.3.1 Receive Shift Register (RSR) .............................................................................. 15.3.2 Receive Data Register (RDR) .............................................................................. 15.3.3 Transmit Data Register (TDR)............................................................................. 15.3.4 Transmit Shift Register (TSR) ............................................................................. 15.3.5 Serial Mode Register (SMR)................................................................................ 15.3.6 Serial Control Register (SCR).............................................................................. 15.3.7 Serial Status Register (SSR) ................................................................................ 15.3.8 Smart Card Mode Register (SCMR) .................................................................... 15.3.9 Bit Rate Register (BRR) ...................................................................................... 15.3.10 IrDA Control Register (IrCR) .............................................................................. 15.3.11 Serial Extension Mode Register (SEMR) ............................................................ Rev. 3.00 Mar 17, 2006 page xxv of l 15.4 Operation in Asynchronous Mode .................................................................................... 15.4.1 Data Transfer Format........................................................................................... 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 15.4.3 Clock.................................................................................................................... 15.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 15.4.5 Data Transmission (Asynchronous Mode)........................................................... 15.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 15.5 Multiprocessor Communication Function......................................................................... 15.5.1 Multiprocessor Serial Data Transmission ............................................................ 15.5.2 Multiprocessor Serial Data Reception ................................................................. 15.6 Operation in Clocked Synchronous Mode ........................................................................ 15.6.1 Clock.................................................................................................................... 15.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 15.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 15.7 Operation in Smart Card Interface Mode.......................................................................... 15.7.1 Pin Connection Example...................................................................................... 15.7.2 Data Format (Except for Block Transfer Mode).................................................. 15.7.3 Block Transfer Mode ........................................................................................... 15.7.4 Receive Data Sampling Timing and Reception Margin....................................... 15.7.5 Initialization ......................................................................................................... 15.7.6 Data Transmission (Except for Block Transfer Mode) ........................................ 15.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................... 15.7.8 Clock Output Control........................................................................................... 15.8 IrDA Operation ................................................................................................................. 15.9 Interrupt Sources............................................................................................................... 15.9.1 Interrupts in Normal Serial Communication Interface Mode .............................. 15.9.2 Interrupts in Smart Card Interface Mode ............................................................. 15.10 Usage Notes ...................................................................................................................... 15.10.1 Module Stop Mode Setting .................................................................................. 15.10.2 Break Detection and Processing .......................................................................... 15.10.3 Mark State and Break Sending............................................................................. 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 15.10.5 Relation between Writes to TDR and the TDRE Flag ......................................... 15.10.6 Restrictions on Use of DMAC or DTC................................................................ 15.10.7 Operation in Case of Mode Transition................................................................. 691 691 693 694 695 696 698 702 703 705 709 709 710 711 714 716 718 718 719 720 720 722 723 726 727 729 733 733 734 735 735 735 736 736 736 736 737 Rev. 3.00 Mar 17, 2006 page xxvi of l Section 16 A/D Converter................................................................................................. 741 16.1 Features ............................................................................................................................. 16.2 Input/Output Pins .............................................................................................................. 16.3 Register Descriptions ........................................................................................................ 16.3.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 16.3.3 A/D Control Register (ADCR) ............................................................................ 16.4 Operation .......................................................................................................................... 16.4.1 Single Mode......................................................................................................... 16.4.2 Scan Mode ........................................................................................................... 16.4.3 Input Sampling and A/D Conversion Time ......................................................... 16.4.4 External Trigger Input Timing............................................................................. 16.5 Interrupt Source ................................................................................................................ 16.6 A/D Conversion Accuracy Definitions ............................................................................. 16.7 Usage Notes ...................................................................................................................... 16.7.1 Module Stop Mode Setting .................................................................................. 16.7.2 Permissible Signal Source Impedance ................................................................. 16.7.3 Influences on Absolute Precision......................................................................... 16.7.4 Setting Range of Analog Power Supply and Other Pins ...................................... 16.7.5 Notes on Board Design ........................................................................................ 16.7.6 Notes on Noise Countermeasures ........................................................................ 741 743 744 744 746 750 752 752 752 753 756 756 757 759 759 759 760 760 760 761 Section 17 D/A Converter................................................................................................. 763 17.1 Features ............................................................................................................................. 17.2 Input/Output Pins .............................................................................................................. 17.3 Register Descriptions ........................................................................................................ 17.3.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) ................................................. 17.3.2 D/A Control Registers 01 and 23 (DACR01, DACR23) ..................................... 17.4 Operation .......................................................................................................................... 17.5 Usage Notes ...................................................................................................................... 17.5.1 Setting for Module Stop Mode............................................................................. 17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 763 765 765 765 766 769 770 770 770 Section 18 RAM .................................................................................................................. 771 Section 19 Flash Memory (F-ZTAT Version) ............................................................ 773 19.1 19.2 19.3 19.4 19.5 Features ............................................................................................................................. Mode Transitions .............................................................................................................. Block Configuration.......................................................................................................... Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 773 774 778 781 781 Rev. 3.00 Mar 17, 2006 page xxvii of l 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 19.5.5 RAM Emulation Register (RAMER)................................................................... On-Board Programming Modes........................................................................................ 19.6.1 Boot Mode ........................................................................................................... 19.6.2 User Program Mode............................................................................................. Flash Memory Emulation in RAM ................................................................................... Flash Memory Programming/Erasing ............................................................................... 19.8.1 Program/Program-Verify ..................................................................................... 19.8.2 Erase/Erase-Verify............................................................................................... 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... Program/Erase Protection ................................................................................................. 19.9.1 Hardware Protection ............................................................................................ 19.9.2 Software Protection.............................................................................................. 19.9.3 Error Protection.................................................................................................... Programmer Mode ............................................................................................................ Power-Down States for Flash Memory............................................................................. Usage Notes ...................................................................................................................... Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 781 783 784 785 786 788 789 792 793 795 796 798 798 800 800 800 800 801 801 802 807 Section 20 Masked ROM .................................................................................................. 809 Section 21 Clock Pulse Generator .................................................................................. 21.1 Register Descriptions ........................................................................................................ 21.1.1 System Clock Control Register (SCKCR) ........................................................... 21.1.2 PLL Control Register (PLLCR) ........................................................................... 21.2 Oscillator........................................................................................................................... 21.2.1 Connecting a Crystal Resonator........................................................................... 21.2.2 External Clock Input ............................................................................................ 21.3 PLL Circuit ....................................................................................................................... 21.4 Frequency Divider ............................................................................................................ 21.5 Usage Notes ...................................................................................................................... 21.5.1 Notes on Clock Pulse Generator .......................................................................... 21.5.2 Notes on Resonator .............................................................................................. 21.5.3 Notes on Board Design ........................................................................................ 811 811 812 813 814 814 815 816 817 817 817 817 818 Section 22 Power-Down Modes...................................................................................... 819 22.1 Register Descriptions ........................................................................................................ 822 22.1.1 Standby Control Register (SBYCR) .................................................................... 822 Rev. 3.00 Mar 17, 2006 page xxviii of l 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 22.2 Operation .......................................................................................................................... 22.2.1 Clock Division Mode........................................................................................... 22.2.2 Sleep Mode .......................................................................................................... 22.2.3 Software Standby Mode....................................................................................... 22.2.4 Hardware Standby Mode ..................................................................................... 22.2.5 Module Stop Mode .............................................................................................. 22.2.6 All-Module-Clocks-Stop Mode ........................................................................... 22.3 Clock Output Control..................................................................................................... 22.4 Usage Notes ...................................................................................................................... 22.4.1 I/O Port Status...................................................................................................... 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period.................. 22.4.3 EXDMAC/DMAC/DTC Module Stop ................................................................ 22.4.4 On-Chip Peripheral Module Interrupts ................................................................ 22.4.5 Writing to MSTPCR ............................................................................................ 824 825 825 826 826 829 830 831 831 832 832 832 832 832 832 Section 23 List of Registers.............................................................................................. 833 23.1 Register Addresses (by functional module, in order of the corresponding section numbers)........................... 833 23.2 Register Bits...................................................................................................................... 844 23.3 Register States in Each Operating Mode........................................................................... 856 Section 24 Electrical Characteristics.............................................................................. 865 24.1 24.2 24.3 24.4 24.5 24.6 24.7 Absolute Maximum Ratings ............................................................................................. DC Characteristics ............................................................................................................ AC Characteristics ............................................................................................................ A/D Conversion Characteristics........................................................................................ D/A Conversion Characteristics........................................................................................ Flash Memory Characteristics........................................................................................... Usage Note........................................................................................................................ 865 866 870 906 906 907 908 Appendix .................................................................................................................................. 909 A. B. C. I/O Port States in Each Pin State....................................................................................... 909 Product Lineup.................................................................................................................. 918 Package Dimensions ......................................................................................................... 919 Index .......................................................................................................................................... 921 Rev. 3.00 Mar 17, 2006 page xxix of l Figures Section 1 Overview Figure 1.1 H8S/2678 Group Internal Block Diagram ........................................................... Figure 1.2 H8S/2678R Group Internal Block Diagram......................................................... Figure 1.3 H8S/2678 Group Pin Arrangement...................................................................... Figure 1.4 H8S/2678R Group Pin Arrangement ................................................................... Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. Figure 2.2 Stack Structure in Normal Mode ......................................................................... Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... Figure 2.4 Stack Structure in Advanced Mode ..................................................................... Figure 2.5 Memory Map ....................................................................................................... Figure 2.6 CPU Registers...................................................................................................... Figure 2.7 Usage of General Registers.................................................................................. Figure 2.8 Stack .................................................................................................................... Figure 2.9 General Register Data Formats (1) ...................................................................... Figure 2.9 General Register Data Formats (2) ...................................................................... Figure 2.10 Memory Data Formats ......................................................................................... Figure 2.11 Instruction Formats (Examples)........................................................................... Figure 2.12 Branch Address Specification in Memory Indirect Mode.................................... Figure 2.13 State Transitions................................................................................................... Section 3 MCU Operating Modes Figure 3.1 H8S/2676 Memory Map (1)................................................................................. Figure 3.1 H8S/2676 Memory Map (2)................................................................................. Figure 3.1 H8S/2676 Memory Map (3)................................................................................. Figure 3.1 H8S/2676 Memory Map (4)................................................................................. Figure 3.2 H8S/2675 Memory Map (1)................................................................................. Figure 3.2 H8S/2675 Memory Map (2)................................................................................. Figure 3.3 H8S/2673 Memory Map (1)................................................................................. Figure 3.3 H8S/2673 Memory Map (2)................................................................................. Figure 3.4 H8S/2670 Memory Map ...................................................................................... Figure 3.5 H8S/2674R Memory Map.................................................................................... 3 4 5 6 25 25 26 27 28 29 30 31 34 35 36 48 52 56 65 66 67 68 69 70 71 72 73 74 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) ....................... 78 Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled) ...................... 79 Figure 4.3 Stack Status after Exception Handling................................................................. 82 Rev. 3.00 Mar 17, 2006 page xxx of l Figure 4.4 Operation when SP Value Is Odd ........................................................................ 83 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 .................................................................................................... Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 .................................................................................................... Figure 5.5 Interrupt Exception Handling............................................................................... Figure 5.6 DTC, DMAC, and Interrupt Controller................................................................ Figure 5.7 Contention between Interrupt Generation and Disabling..................................... Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller ........................................................................ Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)..................... Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) ............................................. Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access)......................................... Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) ............................................... Figure 6.6 Area Divisions ..................................................................................................... Figure 6.7 CSn Signal Output Timing (n = 0 to 7)................................................................ Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) ........................ Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space)....................... Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space........................................................ Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space........................................................ Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) ....... Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)......... Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) ....... Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)......... Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. Figure 6.18 Example of Wait State Insertion Timing ............................................................. Figure 6.19 Example of Read Strobe Timing.......................................................................... Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended.................. Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0) ........................................ Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle (RAST = 0) .......................................................................................................... 86 102 109 111 113 116 118 122 132 134 144 148 153 158 159 159 161 162 163 164 165 166 167 168 170 171 172 176 177 Rev. 3.00 Mar 17, 2006 page xxxi of l Figure 6.23 Figure 6.24 Figure 6.25 Figure 6.26 Figure 6.27 Figure 6.28 Figure 6.29 Figure 6.30 Figure 6.31 Figure 6.32 Figure 6.33 Figure 6.34 Figure 6.35 Figure 6.36 Figure 6.37 Figure 6.38 Figure 6.39 Figure 6.40 Figure 6.41 Figure 6.42 Figure 6.43 Figure 6.44 Figure 6.45 Figure 6.46 Figure 6.47 Figure 6.48 Figure 6.49 Figure 6.50 Figure 6.51 Figure 6.52 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0) ......................................................................................... Example of Timing with One Row Address Output Maintenance State (RAST = 0, CAST = 0) ........................................................................................ Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) ... Example of Wait State Insertion Timing (2-State Column Address Output)....... Example of Wait State Insertion Timing (3-State Column Address Output)....... 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ....... Example of 2-CAS DRAM Connection............................................................... Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)............................ Operation Timing in Fast Page Mode (RAST = 0, CAST = 1)............................ Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) ..... Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) .......... RTCNT Operation ............................................................................................... Compare Match Timing....................................................................................... CBR Refresh Timing ........................................................................................... CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ............. Example of CBR Refresh Timing (CBRM = 1)................................................... Self-Refresh Timing............................................................................................. Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States............................................................................................................ Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) ........................................................................................ Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 (RAST = 0, CAST = 1) ........................................................................................ Relationship between and SDRAM (when PLL frequency multiplication factor is x1 or x2) ..................................... Basic Access Timing of Synchronous DRAM (CAS Latency 1)......................... CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) ........................... Example of Access Timing when Row Address Output Hold State Is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) ....................................... Example of Timing with Two-State Precharge Cycle (TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)......................................... Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1) ....................................................................................... DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2)................................. DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2)........................................................ Example of DQMU and DQML Byte Control..................................................... Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2)....... 178 179 180 182 183 184 185 186 187 188 189 190 191 191 192 193 194 195 196 197 202 203 205 207 209 210 211 212 213 215 Rev. 3.00 Mar 17, 2006 page xxxii of l Figure 6.53 Figure 6.54 Figure 6.55 Figure 6.56 Figure 6.57 Figure 6.58 Figure 6.59 Figure 6.60 Figure 6.61 Figure 6.62 Figure 6.63 Figure 6.64 Figure 6.65 Figure 6.66 Figure 6.67 Figure 6.68 Figure 6.69 Figure 6.70 Figure 6.71 Figure 6.72 Figure 6.73 Figure 6.74 Figure 6.75 Figure 6.76 Figure 6.77 Figure 6.78 Figure 6.79 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) .. 217 Auto Refresh Timing ........................................................................................... 218 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) .................. 219 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)................... 220 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) ........................................................................................ 221 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) ..... 222 Synchronous DRAM Mode Setting Timing ........................................................ 223 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1......... 225 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0......... 227 Example of Timing when the Read Data Is Extended by Two States (DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)................. 228 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) .......... 230 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) .......... 231 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)......... 232 Example of Idle Cycle Operation (Write after Read) .......................................... 233 Example of Idle Cycle Operation (Read after Write) .......................................... 234 Relationship between Chip Select (CS) and Read (RD) ...................................... 235 Example of DRAM Full Access after External Read (CAST = 0)....................... 235 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....... 236 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 236 Example of Synchronous DRAM Full Access after External Read (CAS Latency 2) .................................................................................................. 237 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2)................................................................................. 238 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2)................................................................................. 239 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2)................................................... 240 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....... 241 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) ........................................ 242 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)..................................................... 243 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) ......... 244 Rev. 3.00 Mar 17, 2006 page xxxiii of l Figure 6.80 Figure 6.81 Figure 6.82 Figure 6.83 Figure 6.84 Figure 6.85 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) .................. Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode................................. Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) ................................................................. Example of Timing when Write Data Buffer Function is Used........................... Bus Released State Transition Timing................................................................. Bus Release State Transition Timing when Synchronous DRAM Interface........ 245 247 248 250 253 254 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC.................................................................................... Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A).......................................... Figure 7.3 Operation in Sequential Mode ............................................................................. Figure 7.4 Example of Sequential Mode Setting Procedure.................................................. Figure 7.5 Operation in Idle Mode........................................................................................ Figure 7.6 Example of Idle Mode Setting Procedure ............................................................ Figure 7.7 Operation in Repeat mode ................................................................................... Figure 7.8 Example of Repeat Mode Setting Procedure ....................................................... Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) ......... Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is Specified) ................................................................. Figure 7.11 Operation in Normal Mode.................................................................................. Figure 7.12 Example of Normal Mode Setting Procedure ...................................................... Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0).............................................. Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1).............................................. Figure 7.15 Operation Flow in Block Transfer Mode ............................................................. Figure 7.16 Example of Block Transfer Mode Setting Procedure .......................................... Figure 7.17 Example of DMA Transfer Bus Timing .............................................................. Figure 7.18 Example of Short Address Mode Transfer........................................................... Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) ....................................... Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ...................................... Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) ....................... Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ............. Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer ................ Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer .... Figure 7.26 Example of Single Address Mode Transfer (Byte Read)..................................... Figure 7.27 Example of Single Address Mode (Word Read) Transfer ................................... Figure 7.28 Example of Single Address Mode Transfer (Byte Write) .................................... Rev. 3.00 Mar 17, 2006 page xxxiv of l 260 284 291 292 293 294 296 297 299 300 302 303 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Figure 7.29 Figure 7.30 Figure 7.31 Figure 7.32 Figure 7.33 Figure 7.34 Figure 7.35 Figure 7.36 Figure 7.37 Figure 7.38 Figure 7.39 Figure 7.40 Figure 7.41 Example of Single Address Mode Transfer (Word Write) .................................. Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer Example of DREQ Pin Low Level Activated Single Address Mode Transfer .... Example of Dual Address Transfer Using Write Data Buffer Function .............. Example of Single Address Transfer Using Write Data Buffer Function............ Example of Multi-Channel Transfer .................................................................... Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt.................................................................................................. Example of Procedure for Forcibly Terminating DMAC Operation ................... Example of Procedure for Clearing Full Address Mode...................................... Block Diagram of Transfer End/Transfer Break Interrupt................................... DMAC Register Update Timing .......................................................................... Contention between DMAC Register Update and CPU Read ............................. Example in Which Low Level Is Not Output at TEND Pin................................. 321 322 323 324 325 326 327 328 328 329 330 331 333 Section 8 EXDMA Controller Figure 8.1 Block Diagram of EXDMAC .............................................................................. Figure 8.2 Example of Timing in Dual Address Mode ......................................................... Figure 8.3 Data Flow in Single Address Mode ..................................................................... Figure 8.4 Example of Timing in Single Address Mode....................................................... Figure 8.5 Example of Timing in Cycle Steal Mode............................................................. Figure 8.6 Examples of Timing in Burst Mode..................................................................... Figure 8.7 Examples of Timing in Normal Transfer Mode................................................... Figure 8.8 Example of Timing in Block Transfer Mode....................................................... Figure 8.9 Example of Repeat Area Function Operation ...................................................... Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode............... Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode .................................................................................... Figure 8.12 Procedure for Changing Register Settings in Operating Channel ........................ Figure 8.13 Example of Channel Priority Timing................................................................... Figure 8.14 Examples of Channel Priority Timing ................................................................. Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer....................... Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer ................................ Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer ......................... Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge...... Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge......................................................................................................... Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level......... Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level ............................................................................................................ Figure 8.22 Example of Single Address Mode (Byte Read) Transfer..................................... 336 352 353 354 356 357 358 359 360 361 364 365 367 368 369 370 371 372 373 374 375 376 Rev. 3.00 Mar 17, 2006 page xxxv of l Figure 8.23 Figure 8.24 Figure 8.25 Figure 8.26 Figure 8.27 Figure 8.28 Figure 8.29 Figure 8.30 Figure 8.31 Figure 8.32 Figure 8.33 Figure 8.34 Figure 8.35 Figure 8.36 Figure 8.37 Figure 8.38 Figure 8.39 Figure 8.40 Figure 8.41 Figure 8.42 Figure 8.43 Figure 8.44 Example of Single Address Mode (Word Read) Transfer ................................... Example of Single Address Mode (Byte Write) Transfer.................................... Example of Single Address Mode (Word Write) Transfer .................................. Example of Single Address Mode Transfer Activated by EDREQ Pin Falling Edge......................................................................................................... Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level ............................................................................................................ Auto Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode) .................................................................. Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode).................................................................... Auto Request/Cycle Steal Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) ................................. Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 0) .................................................... Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 1) .................................................... Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/BGUP = 1).................................................. Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) ................................. External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing) .................................. External Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing).................................... External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing)............................. External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing ......................... External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) ................ External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)........... External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0).................. External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) .................... External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1).................. External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing).... 376 377 377 378 379 380 381 381 382 382 383 383 384 385 385 386 387 388 389 390 391 392 Rev. 3.00 Mar 17, 2006 page xxxvi of l Figure 8.45 Figure 8.46 Transfer End Interrupt Logic ............................................................................... 395 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred ........................................................................................ 397 Section 9 Data Transfer Controller (DTC) Figure 9.1 Block Diagram of DTC........................................................................................ Figure 9.2 Block Diagram of DTC Activation Source Control............................................. Figure 9.3 Correspondence between DTC Vector Address and Register Information.......... Figure 9.4 Flowchart of DTC Operation ............................................................................... Figure 9.5 Memory Mapping in Normal Mode..................................................................... Figure 9.6 Memory Mapping in Repeat Mode...................................................................... Figure 9.7 Memory Mapping in Block Transfer Mode ......................................................... Figure 9.8 Operation of Chain Transfer ................................................................................ Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................ Figure 9.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ........................................................................................... Figure 9.11 DTC Operation Timing (Example of Chain Transfer)......................................... Figure 9.12 Chain Transfer when Counter = 0........................................................................ Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.1 Block Diagram of TPU ........................................................................................ Figure 11.2 Example of Counter Operation Setting Procedure............................................... Figure 11.3 Free-Running Counter Operation......................................................................... Figure 11.4 Periodic Counter Operation ................................................................................. Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match .......... Figure 11.6 Example of 0 Output/1 Output Operation............................................................ Figure 11.7 Example of Toggle Output Operation.................................................................. Figure 11.8 Example of Setting Procedure for Input Capture Operation ................................ Figure 11.9 Example of Input Capture Operation ................................................................... Figure 11.10 Example of Synchronous Operation Setting Procedure ....................................... Figure 11.11 Example of Synchronous Operation .................................................................... Figure 11.12 Compare Match Buffer Operation ....................................................................... Figure 11.13 Input Capture Buffer Operation ........................................................................... Figure 11.14 Example of Buffer Operation Setting Procedure ................................................. Figure 11.15 Example of Buffer Operation (1) ......................................................................... Figure 11.16 Example of Buffer Operation (2) ......................................................................... Figure 11.17 Cascaded Operation Setting Procedure................................................................ Figure 11.18 Example of Cascaded Operation (1) .................................................................... Figure 11.19 Example of Cascaded Operation (2) .................................................................... Figure 11.20 Example of PWM Mode Setting Procedure......................................................... Figure 11.21 Example of PWM Mode Operation (1)................................................................ 402 407 408 411 413 414 415 416 417 417 418 424 524 559 560 561 561 562 562 563 564 565 566 567 567 568 569 570 571 571 572 574 575 Rev. 3.00 Mar 17, 2006 page xxxvii of l Figure 11.22 Figure 11.23 Figure 11.24 Figure 11.25 Figure 11.26 Figure 11.27 Figure 11.28 Figure 11.29 Figure 11.30 Figure 11.31 Figure 11.32 Figure 11.33 Figure 11.34 Figure 11.35 Figure 11.36 Figure 11.37 Figure 11.38 Figure 11.39 Figure 11.40 Figure 11.41 Figure 11.42 Figure 11.43 Figure 11.44 Figure 11.45 Figure 11.46 Figure 11.47 Figure 11.48 Figure 11.49 Figure 11.50 Figure 11.51 Figure 11.52 Figure 11.53 Example of PWM Mode Operation (2)................................................................ Example of PWM Mode Operation (3)................................................................ Example of Phase Counting Mode Setting Procedure ......................................... Example of Phase Counting Mode 1 Operation................................................... Example of Phase Counting Mode 2 Operation................................................... Example of Phase Counting Mode 3 Operation................................................... Example of Phase Counting Mode 4 Operation................................................... Phase Counting Mode Application Example ....................................................... Count Timing in Internal Clock Operation .......................................................... Count Timing in External Clock Operation ......................................................... Output Compare Output Timing .......................................................................... Input Capture Input Signal Timing ...................................................................... Counter Clear Timing (Compare Match)............................................................. Counter Clear Timing (Input Capture)................................................................. Buffer Operation Timing (Compare Match) ........................................................ Buffer Operation Timing (Input Capture)............................................................ TGI Interrupt Timing (Compare Match).............................................................. TGI Interrupt Timing (Input Capture).................................................................. TCIV Interrupt Setting Timing ............................................................................ TCIU Interrupt Setting Timing ............................................................................ Timing for Status Flag Clearing by CPU............................................................. Timing for Status Flag Clearing by DTC/DMAC Activation .............................. Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... Contention between TCNT Write and Clear Operations ..................................... Contention between TCNT Write and Increment Operations.............................. Contention between TGR Write and Compare Match ......................................... Contention between Buffer Register Write and Compare Match ........................ Contention between TGR Read and Input Capture.............................................. Contention between TGR Write and Input Capture............................................. Contention between Buffer Register Write and Input Capture ............................ Contention between Overflow and Counter Clearing .......................................... Contention between TCNT Write and Overflow ................................................. 575 576 577 578 579 580 581 582 586 586 587 587 588 588 589 589 590 591 592 592 593 593 594 595 596 597 598 599 600 601 602 603 Section 12 Programmable Pulse Generator (PPG) Figure 12.1 Block Diagram of PPG ........................................................................................ Figure 12.2 Overview Diagram of PPG .................................................................................. Figure 12.3 Timing of Transfer and Output of NDR Contents (Example).............................. Figure 12.4 Setup Procedure for Normal Pulse Output (Example) ......................................... Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output).................................. Figure 12.6 Non-Overlapping Pulse Output............................................................................ Figure 12.7 Non-Overlapping Operation and NDR Write Timing.......................................... Rev. 3.00 Mar 17, 2006 page xxxviii of l 606 615 616 617 618 619 620 Figure 12.8 Figure 12.9 Figure 12.10 Figure 12.11 Setup Procedure for Non-Overlapping Pulse Output (Example) ......................... Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............ Inverted Pulse Output (Example)......................................................................... Pulse Output Triggered by Input Capture (Example) .......................................... 621 622 624 625 Section 13 8-Bit Timers (TMR) Figure 13.1 Block Diagram of 8-Bit Timer Module ............................................................... Figure 13.2 Example of Pulse Output ..................................................................................... Figure 13.3 Count Timing for Internal Clock Input ................................................................ Figure 13.4 Count Timing for External Clock Input ............................................................... Figure 13.5 Timing of CMF Setting........................................................................................ Figure 13.6 Timing of Timer Output....................................................................................... Figure 13.7 Timing of Compare Match Clear ......................................................................... Figure 13.8 Timing of Clearance by External Reset ............................................................... Figure 13.9 Timing of OVF Setting ........................................................................................ Figure 13.10 Contention between TCNT Write and Clear........................................................ Figure 13.11 Contention between TCNT Write and Increment ................................................ Figure 13.12 Contention between TCOR Write and Compare Match ...................................... Section 14 Watchdog Timer Figure 14.1 Block Diagram of WDT....................................................................................... Figure 14.2 Operation in Watchdog Timer Mode ................................................................... Figure 14.3 Operation in Interval Timer Mode ....................................................................... Figure 14.4 Writing to TCNT, TCSR, and RSTCSR ............................................................. Figure 14.5 Contention between TCNT Write and Increment ................................................ Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) .................................. Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.1 Block Diagram of SCI ......................................................................................... Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode..................................... Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) ......................................................................................... Figure 15.5 Sample SCI Initialization Flowchart.................................................................... Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. Figure 15.7 Sample Serial Transmission Flowchart................................................................ Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)................................................. Figure 15.9 Sample Serial Reception Data Flowchart (1)....................................................... 628 637 637 638 638 639 639 640 640 643 644 645 650 655 656 657 658 659 663 691 693 694 695 696 697 698 700 Rev. 3.00 Mar 17, 2006 page xxxix of l Figure 15.9 Sample Serial Reception Data Flowchart (2)....................................................... Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)......................................... Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................ Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First)............. Figure 15.15 Sample SCI Initialization Flowchart.................................................................... Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode................. Figure 15.17 Sample Serial Transmission Flowchart................................................................ Figure 15.18 Example of SCI Operation in Reception.............................................................. Figure 15.19 Sample Serial Reception Flowchart ..................................................................... Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections ............................ Figure 15.22 Normal Smart Card Interface Data Format.......................................................... Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)..................................................... Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) ................................................... Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate)............................................................. Figure 15.26 Retransfer Operation in SCI Transmit Mode ....................................................... Figure 15.27 TEND Flag Generation Timing in Transmission Operation ................................ Figure 15.28 Example of Transmission Processing Flow ......................................................... Figure 15.29 Retransfer Operation in SCI Receive Mode......................................................... Figure 15.30 Example of Reception Processing Flow .............................................................. Figure 15.31 Timing for Fixing Clock Output Level ................................................................ Figure 15.32 Clock Halt and Restart Procedure........................................................................ Figure 15.33 Block Diagram of IrDA ....................................................................................... Figure 15.34 IrDA Transmit/Receive Operations ..................................................................... Figure 15.35 Example of Synchronous Transmission Using DTC ........................................... Figure 15.36 Sample Flowchart for Mode Transition during Transmission ............................. Figure 15.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission)..................................................... Figure 15.38 Port Pin States during Mode Transition (Internal Clock, Synchronous Transmission)....................................................... Figure 15.39 Sample Flowchart for Mode Transition during Reception................................... 701 703 704 706 707 708 709 710 712 713 714 715 717 718 719 719 720 721 724 724 725 726 727 728 729 730 731 737 738 739 739 740 Section 16 A/D Converter Figure 16.1 Block Diagram of A/D Converter ........................................................................ 742 Figure 16.2 A/D Conversion Timing ...................................................................................... 754 Rev. 3.00 Mar 17, 2006 page xl of l Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 External Trigger Input Timing............................................................................. A/D Conversion Accuracy Definitions ................................................................ A/D Conversion Accuracy Definitions ................................................................ Example of Analog Input Circuit......................................................................... Example of Analog Input Protection Circuit ....................................................... Analog Input Pin Equivalent Circuit.................................................................... 756 758 758 759 761 762 Section 17 D/A Converter Figure 17.1 Block Diagram of D/A Converter ........................................................................ 764 Figure 17.2 Example of D/A Converter Operation ................................................................. 770 Section 19 Flash Memory (F-ZTAT Version) Figure 19.1 Block Diagram of Flash Memory ....................................................................... Figure 19.2 Flash Memory State Transitions .......................................................................... Figure 19.3 Boot Mode ........................................................................................................... Figure 19.4 User Program Mode............................................................................................. Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) ................... Figure 19.6 256-kbyte Flash Memory Block Configuration (Modes 4, 7, 10, and 11) ........... Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode..................... Figure 19.8 Flowchart for Flash Memory Emulation in RAM................................................ Figure 19.9 Example of RAM Overlap Operation .................................................................. Figure 19.10 Program/Program-Verify Flowchart .................................................................... Figure 19.11 Erase/Erase-Verify Flowchart.............................................................................. Figure 19.12 Power-On/Off Timing (H8S/2678 Group)........................................................... Figure 19.13 Power-On/Off Timing (H8S/2678R Group) ........................................................ Figure 19.14 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) .......................... 774 775 776 777 779 780 793 794 795 797 799 804 805 806 Section 20 Masked ROM Figure 20.1 Block Diagram of 256-kbyte Masked ROM (HD6432676)................................. 809 Figure 20.2 Block Diagram of 128-kbyte Masked ROM (HD6432675)................................. 809 Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673)................................... 810 Section 21 Clock Pulse Generator Figure 21.1 Block Diagram of Clock Pulse Generator............................................................ Figure 21.2 Connection of Crystal Resonator (Example) ....................................................... Figure 21.3 Crystal Resonator Equivalent Circuit................................................................... Figure 21.4 External Clock Input (Examples)......................................................................... Figure 21.5 External Clock Input Timing ............................................................................... Figure 21.6 Note on Board Design for Oscillation Circuit...................................................... Figure 21.7 Recommended External Circuitry for PLL Circuit .............................................. 811 814 814 815 816 818 818 Rev. 3.00 Mar 17, 2006 page xli of l Section 22 Power-Down Modes Figure 22.1 Mode Transitions ................................................................................................. 821 Figure 22.2 Software Standby Mode Application Example.................................................... 829 Figure 22.3 Hardware Standby Mode Timing......................................................................... 830 Section 24 Electrical Characteristics Figure 24.1 Output Load Circuit ............................................................................................. Figure 24.2 System Clock Timing .......................................................................................... Figure 24.3 SDRAM Timing ................................................................................................ Figure 24.4 (1) Oscillation Stabilization Timing........................................................................ Figure 24.4 (2) Oscillation Stabilization Timing........................................................................ Figure 24.5 Reset Input Timing .............................................................................................. Figure 24.6 Interrupt Input Timing ......................................................................................... Figure 24.7 Basic Bus Timing: Two-State Access.................................................................. Figure 24.8 Basic Bus Timing: Three-State Access................................................................ Figure 24.9 Basic Bus Timing: Three-State Access, One Wait............................................... Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended).............. Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............ Figure 24.12 Burst ROM Access Timing: One-State Burst Access .......................................... Figure 24.13 Burst ROM Access Timing: Two-State Burst Access ......................................... Figure 24.14 DRAM Access Timing: Two-State Access.......................................................... Figure 24.15 DRAM Access Timing: Two-State Access, One Wait ........................................ Figure 24.16 DRAM Access Timing: Two-State Burst Access ................................................ Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1).................................... Figure 24.18 DRAM Access Timing: Three-State Access, One Wait ...................................... Figure 24.19 DRAM Access Timing: Three-State Burst Access .............................................. Figure 24.20 CAS-Before-RAS Refresh Timing ...................................................................... Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ........... Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ........... Figure 24.24 External Bus Release Timing............................................................................... Figure 24.25 External Bus Request Output Timing .................................................................. Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)............................. Figure 24.27 Synchronous DRAM Self-Refresh Timing .......................................................... Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2) ............................................ Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access ..... Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access ... Figure 24.31 DMAC and EXDMAC TEND/ETEND Output Timing ...................................... Figure 24.32 DMAC and EXDMAC DREQ/EDREQ Input Timing ........................................ Figure 24.33 EXDMAC EDRAK Output Timing..................................................................... Figure 24.34 I/O Port Input/Output Timing .............................................................................. Rev. 3.00 Mar 17, 2006 page xlii of l 870 871 872 872 873 874 875 879 880 881 882 883 884 885 886 887 888 889 890 891 892 892 893 893 894 894 895 896 897 899 900 901 901 901 903 Figure 24.35 Figure 24.36 Figure 24.37 Figure 24.38 Figure 24.39 Figure 24.40 Figure 24.41 Figure 24.42 Figure 24.43 Figure 24.44 Appendix Figure C.1 Figure C.2 PPG Output Timing ............................................................................................. TPU Input/Output Timing.................................................................................... TPU Clock Input Timing ..................................................................................... 8-Bit Timer Output Timing.................................................................................. 8-Bit Timer Clock Input Timing.......................................................................... 8-Bit Timer Reset Input Timing........................................................................... WDT Output Timing............................................................................................ SCK Clock Input Timing ..................................................................................... SCI Input/Output Timing: Synchronous Mode.................................................... A/D Converter External Trigger Input Timing .................................................... 903 903 904 904 904 904 905 905 905 905 Package Dimensions (FP-144H).......................................................................... 919 Package Dimensions (FP-144G).......................................................................... 920 Rev. 3.00 Mar 17, 2006 page xliii of l Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ 7 Table 1.2 Pin Functions.......................................................................................................... 13 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ Table 2.2 Operation Notation................................................................................................. Table 2.3 Data Transfer Instructions ...................................................................................... Table 2.4 Arithmetic Operations Instructions (1)................................................................... Table 2.4 Arithmetic Operations Instructions (2)................................................................... Table 2.5 Logic Operations Instructions ................................................................................ Table 2.6 Shift Instructions .................................................................................................... Table 2.7 Bit Manipulation Instructions (1) ........................................................................... Table 2.7 Bit Manipulation Instructions (2) ........................................................................... Table 2.8 Branch Instructions ................................................................................................ Table 2.9 System Control Instructions ................................................................................... Table 2.10 Block Data Transfer Instructions ........................................................................... Table 2.11 Addressing Modes.................................................................................................. Table 2.12 Absolute Address Access Ranges .......................................................................... 37 38 39 40 41 42 42 43 44 45 46 47 49 50 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection............................................................................ 58 Table 3.2 Pin Functions in Each Operating Mode.................................................................. 64 Section 4 Exception Handling Table 4.1 Exception Types and Priority ................................................................................. Table 4.2 Exception Handling Vector Table .......................................................................... Table 4.3 Status of CCR and EXR after Trace Exception Handling ...................................... Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling ..................... 75 76 80 81 Section 5 Interrupt Controller Table 5.1 Pin Configuration ................................................................................................... 87 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 103 Table 5.3 Interrupt Control Modes......................................................................................... 107 Table 5.4 Interrupt Response Times....................................................................................... 114 Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses..................... 115 Rev. 3.00 Mar 17, 2006 page xliv of l Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ........................................ Table 6.3 Data Buses Used and Valid Strobes ....................................................................... Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .... Table 6.6 DRAM Interface Pins............................................................................................. Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space ......................................................................................................... Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .... Table 6.9 Synchronous DRAM Interface Pins ....................................................................... Table 6.10 Setting CAS Latency .............................................................................................. Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space.................................................................................... Table 6.12 Pin States in Idle Cycle .......................................................................................... Table 6.13 Pin States in Bus Released State ............................................................................ Section 7 DMA Controller (DMAC) Table 7.1 Pin Configuration ................................................................................................... Table 7.2 Short Address Mode and Full Address Mode (Channel 0)..................................... Table 7.3 DMAC Activation Sources .................................................................................... Table 7.4 DMAC Transfer Modes.......................................................................................... Table 7.5 Register Functions in Sequential Mode.................................................................. Table 7.6 Register Functions in Idle Mode ............................................................................ Table 7.7 Register Functions in Repeat Mode ....................................................................... Table 7.8 Register Functions in Single Address Mode .......................................................... Table 7.9 Register Functions in Normal Mode ...................................................................... Table 7.10 Register Functions in Block Transfer Mode........................................................... Table 7.11 DMAC Channel Priority Order .............................................................................. Table 7.12 Interrupt Sources and Priority Order ...................................................................... Section 8 EXDMA Controller Table 8.1 Pin Configuration ................................................................................................... Table 8.2 EXDMAC Transfer Modes .................................................................................... Table 8.3 EXDMAC Channel Priority Order......................................................................... Table 8.4 Interrupt Sources and Priority Order ...................................................................... 123 155 160 173 174 175 198 199 201 204 246 249 252 261 262 286 288 290 293 295 298 301 304 325 329 337 350 366 395 Section 9 Data Transfer Controller (DTC) Table 9.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ 409 Table 9.2 Chain Transfer Conditions ..................................................................................... 412 Table 9.3 Register Function in Normal Mode........................................................................ 412 Rev. 3.00 Mar 17, 2006 page xlv of l Table 9.4 Table 9.5 Table 9.6 Table 9.7 Register Function in Repeat Mode ......................................................................... Register Function in Block Transfer Mode ............................................................ DTC Execution Status ............................................................................................ Number of States Required for Each Execution Status .......................................... 413 414 418 419 Section 10 I/O Ports Table 10.1 Port Functions ........................................................................................................ Table 10.2 Input Pull-Up MOS States (Port A)........................................................................ Table 10.3 Input Pull-Up MOS States (Port B)........................................................................ Table 10.4 Input Pull-Up MOS States (Port C)........................................................................ Table 10.5 Input Pull-Up MOS States (Port D)........................................................................ Table 10.6 Input Pull-Up MOS States (Port E) ........................................................................ Section 11 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 Table 11.7 Table 11.8 Table 11.9 Table 11.10 Table 11.11 Table 11.12 Table 11.13 Table 11.14 Table 11.15 Table 11.16 Table 11.17 Table 11.18 Table 11.19 Table 11.20 Table 11.21 Table 11.22 Table 11.23 Table 11.24 Table 11.25 Table 11.26 Table 11.27 16-Bit Timer Pulse Unit (TPU) TPU Functions........................................................................................................ Pin Configuration ................................................................................................... CCLR2 to CCLR0 (Channels 0 and 3)................................................................... CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... TPSC2 to TPSC0 (Channel 0)................................................................................ TPSC2 to TPSC0 (Channel 1)................................................................................ TPSC2 to TPSC0 (Channel 2)................................................................................ TPSC2 to TPSC0 (Channel 3)................................................................................ TPSC2 to TPSC0 (Channel 4)................................................................................ TPSC2 to TPSC0 (Channel 5)................................................................................ MD3 to MD0.......................................................................................................... TIORH_0................................................................................................................ TIORL_0 ................................................................................................................ TIOR_1 .................................................................................................................. TIOR_2 .................................................................................................................. TIORH_3................................................................................................................ TIORL_3 ................................................................................................................ TIOR_4 .................................................................................................................. TIOR_5 .................................................................................................................. TIORH_0................................................................................................................ TIORL_0 ................................................................................................................ TIOR_1 .................................................................................................................. TIOR_2 .................................................................................................................. TIORH_3................................................................................................................ TIORL_3 ................................................................................................................ TIOR_4 .................................................................................................................. TIOR_5 .................................................................................................................. 428 489 492 496 499 503 522 525 529 529 530 530 531 531 532 532 534 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 Rev. 3.00 Mar 17, 2006 page xlvi of l Table 11.28 Table 11.29 Table 11.30 Table 11.31 Table 11.32 Table 11.33 Table 11.34 Table 11.35 Table 11.36 Register Combinations in Buffer Operation........................................................... Cascaded Combinations ......................................................................................... PWM Output Registers and Output Pins................................................................ Clock Input Pins in Phase Counting Mode............................................................. Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... TPU Interrupts........................................................................................................ 567 570 573 577 578 579 580 581 584 Section 12 Programmable Pulse Generator (PPG) Table 12.1 Pin Configuration ................................................................................................... 607 Section 13 8-Bit Timers (TMR) Table 13.1 Pin Configuration ................................................................................................... Table 13.2 Clock Input to TCNT and Count Condition ........................................................... Table 13.3 8-Bit Timer Interrupt Sources ................................................................................ Table 13.4 Timer Output Priorities .......................................................................................... Table 13.5 Switching of Internal Clock and TCNT Operation ................................................ 629 632 642 646 647 Section 14 Watchdog Timer Table 14.1 Pin configuration .................................................................................................... 650 Table 14.2 WDT Interrupt Source............................................................................................ 656 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.1 Pin Configuration ................................................................................................... Table 15.2 Relationships between N Setting in BRR and Bit Rate B ...................................... Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) ....................................................................................... Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) ....................................................................................................... Table 15.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... Table 15.11 SSR Status Flags and Receive Data Handling........................................................ 664 679 680 681 682 683 684 684 685 686 687 687 692 699 Rev. 3.00 Mar 17, 2006 page xlvii of l Table 15.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................ 732 Table 15.13 SCI Interrupt Sources ............................................................................................. 734 Table 15.14 SCI Interrupt Sources ............................................................................................. 734 Section 16 A/D Converter Table 16.1 A/D Converter Pins ................................................................................................ Table 16.2 Analog Input Channels and Corresponding ADDR Registers................................ Table 16.3 A/D Conversion Time (Single Mode) .................................................................... Table 16.4 A/D Conversion Time (Scan Mode)....................................................................... Table 16.5 A/D Converter Interrupt Source ............................................................................. Table 16.6 Analog Pin Specifications ...................................................................................... 743 745 754 755 756 762 Section 17 D/A Converter Table 17.1 Pin Configuration ................................................................................................... 765 Table 17.2 Control of D/A Conversion .................................................................................... 767 Table 17.3 Control of D/A Conversion .................................................................................... 769 Section 19 Flash Memory (F-ZTAT Version) Table 19.1 Differences between Boot Mode and User Program Mode.................................... 775 Table 19.2 Pin Configuration ................................................................................................... 781 Table 19.3 Erase Blocks........................................................................................................... 786 Table 19.4 Setting On-Board Programming Modes................................................................. 788 Table 19.5 Boot Mode Operation............................................................................................. 791 Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible............................................................................................................... 792 Table 19.7 Flash Memory Operating States ............................................................................. 801 Section 21 Clock Pulse Generator Table 21.1 Damping Resistance Value .................................................................................... 814 Table 21.2 Crystal Resonator Characteristics........................................................................... 815 Table 21.3 External Clock Input Conditions ............................................................................ 816 Section 22 Power-Down Modes Table 22.1 Operating Modes .................................................................................................... 820 Table 22.2 Oscillation Stabilization Time Settings .................................................................. 828 Table 22.3 Pin State in Each Processing State ...................................................................... 831 Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings................................................................................... 865 Table 24.2 DC Characteristics.................................................................................................. 866 Table 24.3 DC Characteristics.................................................................................................. 868 Rev. 3.00 Mar 17, 2006 page xlviii of l Table 24.4 Table 24.5 Table 24.6 Table 24.7 Table 24.8 Table 24.9 Table 24.10 Table 24.11 Table 24.12 Table 24.13 Permissible Output Currents .................................................................................. Clock Timing ......................................................................................................... Control Signal Timing............................................................................................ Bus Timing............................................................................................................. Bus Timing............................................................................................................. DMAC and EXDMAC Timing .............................................................................. Timing of On-Chip Peripheral Modules................................................................. A/D Conversion Characteristics ............................................................................. D/A Conversion Characteristics ............................................................................. Flash Memory Characteristics................................................................................ 869 871 874 876 877 898 902 906 906 907 Rev. 3.00 Mar 17, 2006 page xlix of l Rev. 3.00 Mar 17, 2006 page l of l Section 1 Overview Section 1 Overview 1.1 Features * High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions * Various peripheral functions DMA controller (DMAC) EXDMA controller (EXDMAC) Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) 10-bit A/D converter 8-bit D/A converter Clock pulse generator * On-chip memory ROM Type Flash memory version Masked ROM version Model HD64F2676 HD6432676 HD6432675 HD6432673 ROMless version HD6412674R HD6412670 ROM 256 kbytes 256 kbytes 128 kbytes 64 kbytes -- -- RAM 8 kbytes 8 kbytes 8 kbytes 8 kbytes 32 kbytes 8 kbytes * General I/O ports I/O pins: 103 Input-only pins: 12 * Supports various power-down states Rev. 3.00 Mar 17, 2006 page 1 of 926 REJ09B0283-0300 Section 1 Overview * Compact package Product H8S/2678 Group H8S/2678R Group Package QFP-144 LQFP-144 (Code) FP-144G FP-144H Mounting Height 3.05 mm (Max.) 1.70 mm (Max.) Body Size 22.0 x 22.0 mm 22.0 x 22.0 mm Pin Pitch 0.5 mm 0.5 mm Rev. 3.00 Mar 17, 2006 page 2 of 926 REJ09B0283-0300 Section 1 Overview 1.2 Block Diagram PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 PLLVcc PLLVss Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Port D PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port E H8S/2600 CPU Clock pulse generator Internal data bus Internal address bus Bus controller MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF FWE*2 NMI PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15 PF1/UCAS/IRQ14 PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3 PG2/CS2 PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/EDACK3/(IRQ5) P84/EDACK2/(IRQ4) P83/ETEND3/(IRQ3) P82/ETEND2/(IRQ2) P81/EDREQ3/(IRQ1) P80/EDREQ2/(IRQ0) PLL PA7/A23 PA6/A22 PA5/A21 PA4/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3 / A11 PB2/A10 PB1/A9 PB0/A8 PC7/ A7 PC6/ A6 PC5/ A5 PC4/ A4 PC3/ A3 PC2/ A2 PC1/ A1 PC0/ A0 DTC EXDMAC Port G RAM WDT Port 3 Port C ROM*1 (Flash memory or mask ROM) DMAC Peripheral address bus Interrupt controller Port F Peripheral data bus Port B Port A TMR x 2 channels Port 6 TPU x 6 channels SCI x 3 channels P35/ SCK1/(OE) P34/ SCK0 P33/ RxD1 P32/ RxD0/IrRxD P31/ TxD1 P30/ TxD0/IrTxD P57/ AN15/DA3/IRQ7 P56/ AN14/DA2/IRQ6 P55/ AN13/IRQ5 P54/ AN12/IRQ4 P53/ ADTRG//IRQ3 P52/ SCK2/IRQ2 P51/ RxD2/IRQ1 P50/ TxD2/IRQ0 PPG Port 8 10-bit A/D converter Port 1 Port 2 Port 4 Port 5 8-bit D/A converter Port 7 Port H Vref AVcc AVss P10/ PO8 /TIOCA0 P11/ PO9 /TIOCB0 P12/ PO10 /TIOCC0 /TCLKA P13/ PO11 /TIOCD0 /TCLKB P14 /PO12 /TIOCA1 P15/ PO13 /TIOCB1 / TCLKC P16/ PO14 / TIOCA2/EDRAK2 P17 / PO15/ TIOCB2 / TCLKD/EDRAK3 P47 / AN7/ DA1 P46 / AN6/ DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Notes: 1. ROM is not supported in the ROMless version. 2. The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin. Figure 1.1 H8S/2678 Group Internal Block Diagram Rev. 3.00 Mar 17, 2006 page 3 of 926 REJ09B0283-0300 P20 /PO0/ TIOCA3/(IRQ8) P21 /PO1/ TIOCB3/(IRQ9) P22 /PO2 /TIOCC3 / (IRQ10) P23 /PO3 /TIOCD3 / (IRQ11) P24/PO4 /TIOCA4 / (IRQ12) P25/PO5 /TIOCB4 / (IRQ13) P26 /PO6/ TIOCA5 /EDRAK0/(IRQ14) P27 /PO7/ TIOCB5 /EDRAK1/(IRQ15) P75 /EDACK1/(DACK1) P74 /EDACK0/(DACK0) P73/ETEND1/(TEND1) P72/ETEND0/(TEND0) P71/EDREQ1/(DREQ1) P70/EDREQ0/(DREQ0) PH3/CS7/OE/(IRQ7) PH2/CS6/(IRQ6) PH1/CS5 PH0/CS4 Section 1 Overview PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port D PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Vcc Vcc Vcc Vcc Vcc PLLVcc PLLVss Vss Vss Vss Vss Vss Vss Vss Vss Port E Bus controller MD2 MD1 MD0 DCTL EXTAL XTAL STBY RES WDTOVF NMI PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15/DQML PF1/UCAS/IRQ14/DQMU PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P85/EDACK3/(IRQ5) P84/EDACK2/(IRQ4) P83/ETEND3/(IRQ3) P82/ETEND2/(IRQ2) P81/EDREQ3/(IRQ1) P80/EDREQ2/(IRQ0) H8S/2600 CPU Clock pulse generator Internal address bus PLL Internal data bus PA7/A23 PA6/A22 PA5/A21 PA4/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3 / A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/(OE)/(CKE) P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P57/AN15/DA3/IRQ7 P56/AN14/DA2/IRQ6 P55/AN13/IRQ5 P54/AN12/IRQ4 P53/ADTRG//IRQ3 P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0 DMAC ROM* (Flash memory) Peripheral address bus Interrupt controller DTC Peripheral data bus Port F Port G EXDMAC RAM WDT Port 3 TMR x 2 channels Port 6 TPU x 6 channels SCI x 3 channels PPG Port 8 10-bit A/D converter Port 1 Port 2 Port 4 Port 5 8-bit D/A converter Port C Port B Port A Port 7 Port H P10/ PO8 / TIOCA0 P11 / PO9 / TIOCB0 P12 / PO10 / TIOCC0 / TCLKA P13 / PO11 /TIOCD0 / TCLKB P14 / PO12 / TIOCA1 P15 / PO13 / TIOCB1 / TCLKC P16 / PO14 / TIOCA2/EDRAK2 P17 / PO15 / TIOCB2 / TCLKD/EDRAK3 Vref AVcc AVss Note: * ROM is not supported in the ROMless version. Figure 1.2 H8S/2678R Group Internal Block Diagram Rev. 3.00 Mar 17, 2006 page 4 of 926 REJ09B0283-0300 P20 / PO0 / TIOCA3/(IRQ8) P21 / PO1 / TIOCB3/(IRQ9) P22 / PO2 / TIOCC3 / (IRQ10) P23 / PO3 / TIOCD3 / (IRQ11) P24 / PO4 / TIOCA4 / (IRQ12) P25 / PO5 / TIOCB4 / (IRQ13) P26 / PO6 / TIOCA5 /EDRAK0/(IRQ14) P27 / PO7 / TIOCB5 /EDRAK1/(IRQ15) PH3/CS7/OE/(IRQ7)/CKE PH2/CS6/(IRQ6) PH1/CS5/RAS5/SDRAM PH0/CS4/RAS4/WE P47 / AN7 / DA1 P46 / AN6 / DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 P75 /EDACK1/(DACK1) P74 / EDACK0/(DACK0) P73 / ETEND1/(TEND1) P72 / ETEND0/(TEND0) P71 / EDREQ1/(DREQ1) P70 / EDREQ0/(DREQ0) Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement PLLVcc RES PLLVss PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15 PF1/UCAS/IRQ14 PF0/WAIT P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 PD0 / D8 PD1 / D9 PD2 / D10 PD3 / D11 Vss PD4 / D12 PD5 / D13 PD6 / D14 P51/RxD2/IRQ1 P50/TxD2/IRQ0 PH1/CS5 PH0/CS4 PG3/CS3 PG2/CS2 PG1/CS1 PG0/CS0 STBY Vss XTAL EXTAL Vcc 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PF7/ Notes: 1. The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin. 2. An NC pin should be unconnected. MD2 P83 /ETEND3/(IRQ3) P84 /EDACK2/(IRQ4) P85 /EDACK3/(IRQ5) Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 Vss PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 Vss PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 Vss PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 NC*2 P70 /EDREQ0/(DREQ0) P71 /EDREQ1/(DREQ1) P72 /ETEND0/(TEND0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P52/SCK2/IRQ2 P53/ADTRG/IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/(IRQ7) PG4/BREQO PG5/BACK PG6/BREQ Vcc P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4 P55/AN13/IRQ5 P56/AN14/DA2/IRQ6 P57/AN15/DA3/IRQ7 AVss NC*2 P35/SCK1/(OE) P34/SCK0 P33/RxD1 Vss P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/(IRQ0) P81/EDREQ3/(IRQ1) P82/ETEND2/(IRQ2) MD0 MD1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 FP-144G (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PD7/D15 PE0/D0 PE1/D1 PE2/D2 PE3/D3 Vcc PE4/D4 PE5/D5 PE6/D6 PE7/D7 FWE*1 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P27/PO7/TIOCB5/EDRAK1/(IRQ15) P26/PO6/TIOCA5/EDRAK0/(IRQ14) P25/PO5/TIOCB4/(IRQ13) P24/PO4/TIOCA4/(IRQ12) P23/PO3/TIOCD3/(IRQ11) P22/PO2/TIOCC3/(IRQ10) P21/PO1/TIOCB3/(IRQ9) P20/PO0/TIOCA3/(IRQ8) P17/PO15/TIOCB2/TCLKD/EDRAK3 P16/PO14/TIOCA2/EDRAK2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 Vss P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 P75/EDACK1/(DACK1) P74/EDACK0/(DACK0) P73/ETEND1/(TEND1) Vcc NMI WDTOVF Figure 1.3 H8S/2678 Group Pin Arrangement Rev. 3.00 Mar 17, 2006 page 5 of 926 REJ09B0283-0300 Section 1 Overview 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P51/RxD2/IRQ1 P50/TxD2/IRQ0 PH1/CS5/RAS5/SDRAM PH0/CS4/RAS4/WE PG3/CS3/RAS3/CAS PG2/CS2/RAS2/RAS PG1/CS1 PG0/CS0 STBY Vss XTAL EXTAL Vcc PF7/ PLLVcc RES PLLVss PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/IRQ15/DQML PF1/UCAS/IRQ14/DQMU PF0/WAIT P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 PD0 /D8 PD1 /D9 PD2 /D10 PD3 /D11 Vss PD4 /D12 PD5 /D13 PD6 /D14 Note: * An NC pin should be unconnected. Rev. 3.00 Mar 17, 2006 page 6 of 926 REJ09B0283-0300 MD2 P83 /ETEND3/(IRQ3) P84/EDACK2/(IRQ4) P85/EDACK3/(IRQ5) Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 Vss PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 Vss PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 Vss PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 NC* P70/EDREQ0/(DREQ0) P71/EDREQ1/(DREQ1) P72 /ETEND0/(TEND0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P52/SCK2/IRQ2 P53/ADTRG/IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/(IRQ7) PG4 / BREQO PG5 /BACK PG6 /BREQ Vcc P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 Vref AVcc P44 / AN4 P45 / AN5 P46 / AN6 / DA0 P47 / AN7 / DA1 P54 / AN12/IRQ4 P55 / AN13/IRQ5 P56 / AN14/DA2/IRQ6 P57 / AN15/DA3/IRQ7 AVss DCTL P35 / SCK1/(OE)/(CKE) P34 / SCK0 P33 / RxD1 Vss P32 / RxD0/IrRxD P31 / TxD1 P30 / TxD0/IrTxD P80 /EDREQ2/ (IRQ0) P81 /EDREQ3/ (IRQ1) P82/ETEND2/(IRQ2) MD0 MD1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 FP-144H (Top view) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PD7 / D15 PE0 / D0 PE1 / D1 PE2 / D2 PE3 / D3 Vcc PE4 / D4 PE5 / D5 PE6 / D6 PE7 / D7 Vss P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 P27/ PO7 / TIOCB5/EDRAK1/(IRQ15) P26/ PO6 / TIOCA5/EDRAK0/(IRQ14) P25/ PO5 /TIOCB4 /(IRQ13) P24/ PO4 /TIOCA4 /(IRQ12) P23/ PO3 /TIOCD3 /(IRQ11) P22/ PO2 /TIOCC3 /(IRQ10) P21/PO1/TIOCB3/(IRQ9) P20/PO0/TIOCA3/(IRQ8) P17/ PO15 /TIOCB2/TCLKD/EDRAK3 P16/PO14/TIOCA2/EDRAK2 P15/ PO13 /TIOCB1/TCLKC P14/PO12/TIOCA1 Vss P13/ PO11 /TIOCD0/TCLKB P12/ PO10 /TIOCC0/TCLKA P11/ PO9 /TIOCB0 P10/ PO8 /TIOCA0 P75/EDACK1/(DACK1) P74/EDACK0/(DACK0) P73/ETEND1/(TEND1) Vcc NMI WDTOVF Figure 1.4 H8S/2678R Group Pin Arrangement Section 1 Overview 1.3.2 Table 1.1 Pin Arrangement in Each Operating Mode Pin Arrangement in Each Operating Mode Pin Name Mode 7 Flash Memory Programmer Mode Vss NC Pin No. 1 2 Modes 1 and 5 MD2 P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) Vcc A0 A1 A2 A3 A4 A5 Vss A6 A7 A8 A9 A10 A11 Vss A12 A13 A14 A15 A16 A17 Vss Modes 2 and 6 MD2 P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) Vcc A0 A1 A2 A3 A4 A5 Vss A6 A7 A8 A9 A10 A11 Vss A12 A13 A14 A15 A16 A17 Vss Mode 4 MD2 P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 Vss PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 Vss PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 Vss EXPE = 1 MD2 P83/ETEND3/ (IRQ3) P84/EDACK2/ (IRQ4) P85/EDACK3/ (IRQ5) Vcc PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 Vss PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 Vss PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 Vss EXPE = 0 MD2 P83/(IRQ3) 3 P84/(IRQ4) NC 4 P85/(IRQ5) NC 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Vcc PC0 PC1 PC2 PC3 PC4 PC5 Vss PC6 PC7 PB0 PB1 PB2 PB3 Vss PB4 PB5 PB6 PB7 PA0 PA1 Vss Vcc A0 A1 A2 A3 A4 A5 Vss A6 A7 A8 A9 A10 A11 Vss A12 A13 A14 A15 A16 A17 Vss Rev. 3.00 Mar 17, 2006 page 7 of 926 REJ09B0283-0300 Section 1 Overview Pin Name Mode 7 Pin No. 27 28 29 30 31 32 33 34 Modes 1 and 5 A18 A19 A20 PA5/A21 PA6/A22 PA7/A23 NC P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF NMI Vcc P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB Vss P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 Modes 2 and 6 A18 A19 A20 PA5/A21 PA6/A22 PA7/A23 NC P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF NMI Vcc P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB Vss P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 Mode 4 PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 NC P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF NMI Vcc P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB Vss P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 EXPE = 1 PA2/A18 PA3/A19 PA4/A20 PA5/A21 PA6/A22 PA7/A23 NC P70/EDREQ0/ (DREQ0) P71/EDREQ1/ (DREQ1) P72/ETEND0/ (TEND0) WDTOVF NMI Vcc P73/ETEND1/ (TEND1) P74/EDACK0/ (DACK0) P75/EDACK1/ (DACK1) P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB Vss P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2/EDRAK2 EXPE = 0 PA2 PA3 PA4 PA5 PA6 PA7 NC P70/(DREQ0) Flash Memory Programmer Mode A18 NC NC NC NC NC NC NC 35 P71/(DREQ1) NC 36 P72/(TEND0) WDTOVF NMI Vcc P73/(TEND1) NC 37 38 39 40 NC Vcc Vcc NC 41 P74/(DACK0) NC 42 P75/(DACK1) NC 43 44 45 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/ TIOCC0/TCLKA P13/PO11/ TIOCD0/TCLKB Vss P14/PO12/ TIOCA1 P15/PO13/ TIOCB1/TCLKC P16/PO14/ TIOCA2 NC NC NC 46 NC 47 48 Vss NC 49 NC 50 NC Rev. 3.00 Mar 17, 2006 page 8 of 926 REJ09B0283-0300 Section 1 Overview Pin Name Mode 7 Pin No. 51 Modes 1 and 5 P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*2 D7 D6 D5 D4 Vcc D3 D2 D1 D0 D15 Modes 2 and 6 P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*2 PE7/D7 PE6/D6 PE5/D5 PE4/D4 Vcc PE3/D3 PE2/D2 PE1/D1 PE0/D0 D15 Mode 4 P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*2 PE7/D7 PE6/D6 PE5/D5 PE4/D4 Vcc PE3/D3 PE2/D2 PE1/D1 PE0/D0 D15 EXPE = 1 P17/PO15/ TIOCB2/TCLKD/ EDRAK3 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/ EDRAK0/(IRQ14) P27/PO7/ TIOCB5/ EDRAK1/(IRQ15) P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*2 PE7/D7 PE6/D6 PE5/D5 PE4/D4 Vcc PE3/D3 PE2/D2 PE1/D1 PE0/D0 D15 EXPE = 0 P17/PO15/ TIOCB2/TCLKD Flash Memory Programmer Mode NC 52 P20/PO0/ TIOCA3/(IRQ8) P21/PO1/ TIOCB3/(IRQ9) P22/PO2/ TIOCC3/(IRQ10) P23/PO3/ TIOCD3/(IRQ11) P24/PO4/ TIOCA4/(IRQ12) P25/PO5/ TIOCB4/(IRQ13) P26/PO6/ TIOCA5/(IRQ14) NC 53 NC OE CE WE 54 55 56 57 Vss 58 NC 59 P27/PO7/ TIOCB5/(IRQ15) NC 60 P60/TMRI0/ DREQ0/IRQ8 P61/TMRI1/ DREQ1/IRQ9 FWE*1 Vss*2 PE7 PE6 PE5 PE4 Vcc PE3 PE2 PE1 PE0 PD7 NC 61 NC FWE*1 Vss*2 NC NC NC NC Vcc NC NC NC NC I/O7 62 63 64 65 66 67 68 69 70 71 72 Rev. 3.00 Mar 17, 2006 page 9 of 926 REJ09B0283-0300 Section 1 Overview Pin Name Mode 7 Pin No. 73 74 75 76 77 78 79 80 81 Modes 1 and 5 D14 D13 D12 Vss D11 D10 D9 D8 P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU*2 PF2/LCAS/ IRQ15/DQML*2 PF3/LWR HWR RD PF6/AS PLLVss RES PLLVcc PF7/ Vcc EXTAL XTAL Vss STBY Modes 2 and 6 D14 D13 D12 Vss D11 D10 D9 D8 P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU*2 PF2/LCAS/ IRQ15/DQML*2 PF3/LWR HWR RD PF6/AS PLLVss RES PLLVcc PF7/ Vcc EXTAL XTAL Vss STBY Mode 4 D14 D13 D12 Vss D11 D10 D9 D8 P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU*2 PF2/LCAS/ IRQ15/DQML*2 PF3/LWR HWR RD PF6/AS PLLVss RES PLLVcc PF7/ Vcc EXTAL XTAL Vss STBY EXPE = 1 D14 D13 D12 Vss D11 D10 D9 D8 P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0/WAIT PF1/UCAS/ IRQ14/DQMU*2 PF2/LCAS/ IRQ15/DQML*2 PF3/LWR HWR RD PF6/AS PLLVss RES PLLVcc PF7/ Vcc EXTAL XTAL Vss STBY EXPE = 0 PD6 PD5 PD4 Vss PD3 PD2 PD1 PD0 P62/TMCI0/ TEND0/IRQ10 P63/TMCI1/ TEND1/IRQ11 P64/TMO0/ DACK0/IRQ12 P65/TMO1/ DACK1/IRQ13 PF0 PF1/IRQ14 Flash Memory Programmer Mode I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 I/O0 NC 82 NC 83 NC 84 NC 85 86 NC NC 87 PF2/IRQ15 NC 88 89 90 91 92 93 94 95 96 97 98 99 100 PF3 PF4 PF5 PF6 PLLVss RES PLLVcc PF7/ Vcc EXTAL XTAL Vss STBY NC NC NC NC Vss RES Vcc NC Vcc EXTAL XTAL Vss Vcc Rev. 3.00 Mar 17, 2006 page 10 of 926 REJ09B0283-0300 Section 1 Overview Pin Name Mode 7 Pin No. 101 102 103 Modes 1 and 5 PG0/CS0 PG1/CS1 PG2/CS2/ RAS2*2/RAS*2 PG3/CS3/ 2 2 RAS3* /CAS* PH0/CS4/ RAS4*2/WE*2 PH1/CS5/ 2 RAS5* / SDRAM*2 P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*2 PG4/BREQO PG5/BACK PG6/BREQ Vcc P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4 Modes 2 and 6 PG0/CS0 PG1/CS1 PG2/CS2/ RAS2*2/RAS*2 PG3/CS3/ 2 2 RAS3* /CAS* PH0/CS4/ RAS4*2/WE*2 PH1/CS5/ 2 RAS5* / SDRAM*2 P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*2 PG4/BREQO PG5/BACK PG6/BREQ Vcc P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4 Mode 4 PG0/CS0 PG1/CS1 PG2/CS2/ RAS2*2/RAS*2 PG3/CS3/ 2 2 RAS3* /CAS* PH0/CS4/ RAS4*2/WE*2 PH1/CS5/ 2 RAS5* / SDRAM*2 P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*2 PG4/BREQO PG5/BACK PG6/BREQ Vcc P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4 EXPE = 1 PG0/CS0 PG1/CS1 PG2/CS2/ RAS2*2/RAS*2 PG3/CS3/ 2 2 RAS3* /CAS* PH0/CS4/ RAS4*2/WE*2 PH1/CS5/ 2 RAS5* / SDRAM*2 P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/CS6/(IRQ6) PH3/CS7/OE/ (IRQ7)/CKE*2 PG4/BREQO PG5/BACK PG6/BREQ Vcc P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4 EXPE = 0 PG0 PG1 PG2 Flash Memory Programmer Mode NC NC NC 104 PG3 NC 105 PH0 NC 106 PH1 NC 107 108 109 110 P50/TxD2/IRQ0 P51/RxD2/IRQ1 P52/SCK2/IRQ2 P53/ADTRG/ IRQ3 PH2/(IRQ6) PH3/(IRQ7) Vss Vss Vcc NC 111 112 NC NC 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 PG4 PG5 PG6 Vcc P40/AN0 P41/AN1 P42/AN2 P43/AN3 Vref AVcc P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P54/AN12/IRQ4 NC NC NC Vcc NC NC NC NC NC Vcc NC NC NC NC NC Rev. 3.00 Mar 17, 2006 page 11 of 926 REJ09B0283-0300 Section 1 Overview Pin Name Mode 7 Pin No. 128 129 Modes 1 and 5 P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss 3 NC* 2 DCTL* Modes 2 and 6 P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss 3 NC* 2 DCTL* Mode 4 P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss 3 NC* 2 DCTL* EXPE = 1 P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss 3 NC* 2 DCTL* EXPE = 0 P55/AN13/IRQ5 P56/AN14/DA2/ IRQ6 P57/AN15/DA3/ IRQ7 AVss 3 NC* 2 DCTL* Flash Memory Programmer Mode NC NC 130 NC 131 132 Vss NC* 2 Vss * 3 133 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 Vss P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2) MD0 MD1 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 Vss P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2) MD0 MD1 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 Vss P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2) MD0 MD1 P35/SCK1/(OE)/ (CKE)*2 P34/SCK0 P33/RxD1 Vss P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/EDREQ2/ (IRQ0) P81/EDREQ3/ (IRQ1) P82/ETEND2/ (IRQ2) MD0 MD1 P35/SCK1 NC 134 135 136 137 138 139 140 P34/SCK0 P33/RxD1 Vss P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P80/(IRQ0) NC NC Vss Vcc NC NC NC 141 P81/(IRQ1) NC 142 P82/(IRQ2) NC 143 144 MD0 MD1 Vss Vss Notes: 1. The FWE pin is used only in the flash memory version of the H8S/2678 Group. In the masked ROM and ROMless versions of the H8S/2678 Group, this is an NC pin. 2. Only for the H8S/2678R Group. 3. Only for the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 12 of 926 REJ09B0283-0300 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) 5, 39, 67, 96, 116 5, 39, 67, 96, 116 Input Type Power supply Symbol VCC Function For connection to the power supply. All VCC pins should be connected to the system power supply. For connection to ground. All VSS pins should be connected to the system power supply (0 V). Power supply pin for the on-chip PLL oscillator. Ground pin for the on-chip PLL oscillator. For connection to a crystal oscillator. See section 21, Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input. For connection to a crystal oscillator. The EXTAL pin can also input an external clock. See section 21, Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input. VSS 12, 19, 26, 12, 19, 26, 47, 76, 99, 47, 76, 99, 136 136 94 92 98 94 92 98 Input PLLVCC PLLVSS Clock XTAL Input Input Input EXTAL 97 97 Input 95 95 106 Output Supplies the system clock to external devices. Output When a synchronous DRAM is connected, this pin is connected to the CLK pin of the synchronous DRAM. For details, refer to section 6, Bus Controller (BSC). Input These pins set the operating mode. These pins should not be changed while the MCU is operating. SDRAM -- Operating mode control MD2 MD1 MD0 1, 144, 143 1, 144, 143 Rev. 3.00 Mar 17, 2006 page 13 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) -- 132 Input Type Operating mode control Symbol DCTL Function When this pin is driven high, SDRAM dedicated to the synchronous DRAM is output. When not using the synchronous DRAM interface, drive this pin low. The level of this pin must not be changed during operation. System control RES STBY 93 100 93 100 Input Input When this pin is driven low, the chip is reset. When this pin is driven low, a transition is made to hardware standby mode. Requests chip to release the bus to an external bus master. BREQ BREQO 115 113 115 113 Input Output External bus request signal used when an internal bus master accesses external space when the external bus is released. Output Indicates that the bus has been released to an external bus master. Input Enables/disables flash memory. This pin is only used in the flash memory version. BACK FWE 114 62 114 -- Address bus A23 to A0 32 to 27, 25 to 20, 18 to 13, 11 to 6 72 to 75, 77 to 80, 63 to 66, 68 to 71 32 to 27, 25 to 20, 18 to 13, 11 to 6 72 to 75, 77 to 80, 63 to 66, 68 to 71 Output These pins output an address. Data bus D15 to D0 Input/ output These pins constitute a bidirectional data bus. Bus control CS7 to CS0 AS 112, 111, 112, 111, 106 to 101 106 to 101 91 91 Output Signals that select division areas 7 to 0 in the external address space. Output When this pin is low, it indicates that address output on the address bus is valid. Rev. 3.00 Mar 17, 2006 page 14 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) 90 90 Type Bus control Symbol RD Function Output When this pin is low, it indicates that the external address space is being read. Output Strobe signal indicating that external address space is to be written, and the upper half (D15 to D8) of the data bus is enabled. Write enable signal for DRAM interface space. HWR 89 89 LWR 88 88 Output Strobe signal indicating that external address space is to be written, and the lower half (D7 to D0) of the data bus is enabled. Output Upper column address strobe signal for 16-bit DRAM interface space. Column address strobe signal for 8bit DRAM interface space. UCAS 86 86 LCAS DQMU 87 -- 87 86 Output Lower column address strobe signal for 16-bit DRAM interface space. Output Upper data mask enable signal for 16-bit synchronous DRAM for 16-bit synchronous DRAM interface. Data mask enable signal for 8-bit synchronous DRAM interface space. DQML -- 87 Output Lower-data mask enable signal for 16-bit synchronous DRAM interface space. Output Row address strobe signal for the synchronous DRAM interface. RAS signal is a row address strobe signal when areas 2 to 5 are set to the continuous DRAM space. RAS/ RAS2 RAS3 to RAS5 RAS -- 103 to 106 -- 103 Row address strobe signal for the synchronous DRAM of the synchronous DRAM interface. Rev. 3.00 Mar 17, 2006 page 15 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) -- 104 Type Bus control Symbol CAS Function Output Column address strobe signal for the synchronous DRAM of the synchronous DRAM interface. Output Write enable signal for the synchronous DRAM of the synchronous DRAM interface. Input Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. WE -- 105 WAIT 85 85 OE (OE) 112, 133 112, 133 Output Output enable signal for DRAM interface space. The output pins of OE and (OE) are selected by the port function control register 2 (PFCR2) of port 3. CKE (CKE) -- 112, 133 Output Clock enable signal of the synchronous DRAM interface space. The output pins of CKE and (CKE) are selected by the port function control register 2 (PFCR2) of port 3. Interrupt signals NMI 38 38 87, 86, 84 to 81, 61, 60, 130 to 127, 110 to 107 59 to 52, 112, 111, 4 to 2, 142 to 140 61, 60, 35, 34 Input Input Nonmaskable interrupt request pin. Fix high when not used. These pins request a maskable interrupt. The input pins of DREQn and (DREQn) are selected by the IRQ pin select register (ITSR) of the interrupt controller. (n = 0 to 15) IRQ15 to 87, 86, IRQ0 84 to 81, 61, 60, 130 to 127, 110 to 107 (IRQ15) 59 to 52, to (IRQ0) 112, 111, 4 to 2, 142 to 140 DMA controller DREQ1 61, 60, (DMAC) DREQ0 35, 34 (DREQ1) (DREQ0) Input These signals request DMAC activation. The input pins of DREQn and (DREQn) are selected by the IRQ pin select register (ITSR) of the interrupt controller. (n = 0 to 15) Rev. 3.00 Mar 17, 2006 page 16 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) 82, 81, 40, 36 Type Symbol Function DMA controller TEND1 82, 81, (DMAC) TEND0 40, 36 (TEND1) (TEND0) Output These signals indicate the end of DMAC data transfer. The input pins of TENDn and (TENDn) are selected by the port function control register 2 (PFCR2) of port 3. (n = 1, 0) DACK1 84, 83, DACK0 42, 41 (DACK1) (DACK0) 84, 83, 42, 41 Output DMAC single address transfer acknowledge signals. The input pins of DACKn and (DACKn) are selected by the port function control register 2 (PFCR2) of port 3. (n = 1, 0) EXDMA controller (EXDMAC) EDREQ3 141, 140, to 35, 34 EDREQ0 ETEND3 2, 142, to 40, 36 ETEND0 EDACK3 4, 3, 42, to 41 EDACK0 EDRAK3 51, 50, to 59, 58 EDRAK0 141, 140, 35, 34 2, 142, 40, 36 4, 3, 42, 41 51, 50, 59, 58 Input These signals request EXDMAC activation. Output These signals indicate the end of EXDMAC data transfer. Output EXDMAC single address transfer acknowledge signals. Output These signals notify an external device of acceptance and start of execution of a DMA transfer request. Input External clock input pins. 16-bit timer pulse unit (TPU) TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 45, 46, 49, 51 45, 46, 49, 51 43, 44, 45, 46 43, 44, 45, 46 Input/ output TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. 48, 49 48, 49 Input/ output Rev. 3.00 Mar 17, 2006 page 17 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) 50, 51 50, 51 Input/ output Input/ output Type 16-bit timer pulse unit (TPU) Symbol TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 Function TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. TGRA_5 and TGRB_5 input capture input/output compare output/PWM output pins. 52, 53, 54, 55 52, 53, 54, 55 56, 57 56, 57 Input/ output Input/ output TIOCA5, 58, 59 TIOCB5 Programmable PO15 to pulse PO0 generator (PPG) 8-bit timer TMO0 TMO1 TMCI0 TMCI1 TMRI0 TMRI1 Watchdog timer (WDT) Serial communication interface (SCI)/smart card interface (SCI_0 with IrDA function) 51 to 48, 46 to 43, 59 to 52 83, 84 81, 82 60, 61 58, 59 51 to 48, 46 to 43, 59 to 52 83, 84 81, 82 60, 61 37 107, 138, 139 Output Pulse output pins. Output Waveform output pins with output compare function. Input Input External event input pins. Counter reset input pins. WDTOVF 37 TxD2 TxD1 TxD0/ IrTxD RxD2 RxD1 RxD0/ IrRxD SCK2 SCK1 SCK0 107, 138, 139 Output Counter overflow signal output pin in watchdog timer mode. Output Data output pins. 108, 135, 137 108, 135, 137 Input Data input pins. 109, 133, 134 109, 133, 134 Input/ output Clock input/output pins. Rev. 3.00 Mar 17, 2006 page 18 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) 130 to 127, 130 to 127, 126 to 123, 126 to 123, 120 to 117 120 to 117 110 130, 129, 126, 125 122 110 130, 129, 126, 125 122 Input Type A/D converter Symbol AN15 to AN12, AN7 to AN0 ADTRG Function Analog input pins for the A/D converter. Input Pin for input of an external trigger to start A/D conversion. D/A converter DA3 to DA0 Output Analog input pins for the D/A converter. Input The analog power-supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). A/D converter, AVCC D/A converter AVSS 131 131 Input The ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). Vref 121 121 Input The reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). I/O ports P17 to P10 P27 to P20 P35 to P30 P47 to P40 51 to 48, 46 to 43 59 to 52 51 to 48, 46 to 43 59 to 52 Input/ output Input/ output Input/ output Input Eight input/output pins. Eight input/output pins. Six input/output pins. Eight input pins. 133 to 135, 133 to 135, 137 to 139 137 to 139 126 to 123, 126 to 123, 120 to 117 120 to 117 Rev. 3.00 Mar 17, 2006 page 19 of 926 REJ09B0283-0300 Section 1 Overview Pin No. FP-144G FP-144H (H8S/2678 (H8S/2678R I/O Group) Group) 130 to 127 130 to 127 110 to 107 110 to 107 84 to 81, 61, 60 42 to 40, 36 to 34 84 to 81, 61, 60 42 to 40, 36 to 34 Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Type I/O ports Symbol P57 to P54 P53 to P50 P65 to P60 P75 to P70 P85 to P80 PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG6 to PG0 PH3 to PH0 Function Four input pins. Four input/output pins. Six input/output pins. Six input/output pins. Six input/output pins. Eight input/output pins. Eight input/output pins. Eight input/output pins. Eight input/output pins. Eight input/output pins. Eight input/output pins. Seven input/output pins. Four input/output pins. 4 to 2, 4 to 2, 142 to 140 142 to 140 32 to 27, 25, 24 23 to 20, 18 to 15 14, 13, 11 to 6 72 to 75, 77 to 80 63 to 66, 68 to 71 95, 91 to 85 32 to 27, 25, 24 23 to 20, 18 to 15 14, 13, 11 to 6 72 to 75, 77 to 80 63 to 66, 68 to 71 95, 91 to 85 115 to 113, 115 to 113, 104 to 101 104 to 101 112, 111, 106, 105 112, 111, 106, 105 Rev. 3.00 Mar 17, 2006 page 20 of 926 REJ09B0283-0300 Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 3 states 16 / 8-bit register-register divide: 12 states CPUS260A_020020020400 Rev. 3.00 Mar 17, 2006 page 21 of 926 REJ09B0283-0300 Section 2 CPU 16 x 16-bit register-register multiply: 4 states 32 / 16-bit register-register divide: 20 states * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. Rev. 3.00 Mar 17, 2006 page 22 of 926 REJ09B0283-0300 Section 2 CPU * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. * Additional control register One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift and rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 3.00 Mar 17, 2006 page 23 of 926 REJ09B0283-0300 Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI. Rev. 3.00 Mar 17, 2006 page 24 of 926 REJ09B0283-0300 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP (SP*2 ) EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode Rev. 3.00 Mar 17, 2006 page 25 of 926 REJ09B0283-0300 Section 2 CPU 2.2.2 Advanced Mode * Address Space Linear access is provided to a 16-Mbyte maximum address space. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 3.00 Mar 17, 2006 page 26 of 926 REJ09B0283-0300 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) (SP*2 ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 3.00 Mar 17, 2006 page 27 of 926 REJ09B0283-0300 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. Note: Normal mode is not available in this LSI. H'0000 64 kbytes H'FFFF H'00000000 16 Mbytes Program area H'00FFFFFF Cannnot be used in this LSI Data area H'FFFFFFFF (a) Normal Mode* Note: * Normal mode cannot be used in this LSI. (b) Advanced Mode Figure 2.5 Memory Map Rev. 3.00 Mar 17, 2006 page 28 of 926 REJ09B0283-0300 Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 0 EXR T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 Sign extension MACL 0 41 MACH 32 Legend: SP PC EXR T I2 to I0 CCR I UI : Stack pointer : Program counter : Extended register : Trace bit : Interrupt mask bits : Condition-code register : Interrupt mask bit : User bit or interrupt mask bit* H U N Z V C MAC : Half-carry flag : User bit : Negative flag : Zero flag : Overflow flag : Carry flag : Multiply-accumulate register Note: * UI cannot be used as an interrupt mask bit in this LSI. Figure 2.6 CPU Registers Rev. 3.00 Mar 17, 2006 page 29 of 926 REJ09B0283-0300 Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 3.00 Mar 17, 2006 page 30 of 926 REJ09B0283-0300 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.3 Extended Register (EXR) EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions except for the STC instruction is executed, all interrupts including NMI will be masked for three states after execution is completed. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is started each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 -- I2 I1 I0 All 1 1 1 1 -- R/W R/W R/W Reserved These bits are always read as 1. These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Rev. 3.00 Mar 17, 2006 page 31 of 926 REJ09B0283-0300 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. Rev. 3.00 Mar 17, 2006 page 32 of 926 REJ09B0283-0300 Section 2 CPU Bit 2 Bit Name Z Initial Value Undefined R/W R/W Description Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Internal Registers When the reset exception handling loads the start address from the vector address, PC is initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However, the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a reset. Rev. 3.00 Mar 17, 2006 page 33 of 926 REJ09B0283-0300 Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type 1-bit data Register Number RnH Data Format 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 3.00 Mar 17, 2006 page 34 of 926 REJ09B0283-0300 Section 2 CPU Data Type Word data Register Number Rn Data Format 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.00 Mar 17, 2006 page 35 of 926 REJ09B0283-0300 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.10 Memory Data Formats Rev. 3.00 Mar 17, 2006 page 36 of 926 REJ09B0283-0300 Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* LDM, STM 3 3 MOVFPE* , MOVTPE* Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B -- B/W/L 4 8 14 5 9 1 Total: 69 23 Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS B -- TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- -- Block data transfer EEPMOV Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 3.00 Mar 17, 2006 page 37 of 926 REJ09B0283-0300 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 3.00 Mar 17, 2006 page 38 of 926 REJ09B0283-0300 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Note: * L L Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Mar 17, 2006 page 39 of 926 REJ09B0283-0300 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Mar 17, 2006 page 40 of 926 REJ09B0283-0300 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W 1 Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L 2 TAS* B -- MAC CLRMAC LDMAC STMAC -- L Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 3.00 Mar 17, 2006 page 41 of 926 REJ09B0283-0300 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. OR B/W/L XOR B/W/L NOT B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. B/W/L B/W/L B/W/L Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Mar 17, 2006 page 42 of 926 REJ09B0283-0300 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Note: * Size refers to the operand size. B: Byte Rev. 3.00 Mar 17, 2006 page 43 of 926 REJ09B0283-0300 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ( BIXOR B BLD B BILD B BST B BIST B Note: * Size refers to the operand size. B: Byte Rev. 3.00 Mar 17, 2006 page 44 of 926 REJ09B0283-0300 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Rev. 3.00 Mar 17, 2006 page 45 of 926 REJ09B0283-0300 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B -- Size refers to the operand size. B: Byte W: Word Rev. 3.00 Mar 17, 2006 page 46 of 926 REJ09B0283-0300 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- 2.6.2 Basic Instruction Formats The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions. Rev. 3.00 Mar 17, 2006 page 47 of 926 REJ09B0283-0300 Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev. 3.00 Mar 17, 2006 page 48 of 926 REJ09B0283-0300 Section 2 CPU Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 3.00 Mar 17, 2006 page 49 of 926 REJ09B0283-0300 Section 2 CPU 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register indirect with post-increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. Register indirect with pre-decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address Note: * 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Not available in this LSI. Rev. 3.00 Mar 17, 2006 page 50 of 926 REJ09B0283-0300 Section 2 CPU 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI. Rev. 3.00 Mar 17, 2006 page 51 of 926 REJ09B0283-0300 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Normal mode is not available in this LSI. (a) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Mode Rev. 3.00 Mar 17, 2006 page 52 of 926 REJ09B0283-0300 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect (@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 * Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 3.00 Mar 17, 2006 page 53 of 926 REJ09B0283-0300 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Note: * Normal mode is not available in this LSI. Rev. 3.00 Mar 17, 2006 page 54 of 926 REJ09B0283-0300 Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. * Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state the CPU executes program instructions in sequence. * Bus-Released State In a product which has a bus master other than the CPU, such as a direct memory access controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 22, Power-Down Modes. Rev. 3.00 Mar 17, 2006 page 55 of 926 REJ09B0283-0300 Section 2 CPU End of bus request Bus request Program execution state of bu s re Bu qu sr es eq t ue st =0 BY SS EEP tion SL truc ins ion = 1 ruct BY nst SS EP i E SL Bus-released state En d of Re ex qu ce es pt tf ion or ha ex nd ce lin pt g ion ha nd lin g En d Sleep mode t rrup Inte u req est Exception handling state External interrupt request Software standby mode RES = High STBY = High, RES = Low Reset state*1 Reset state Hardware standby mode*2 Power down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. In every state, when the STBY pin becomes low, the hardware standby mode is entered. 3. For details, refer to section 22, Power-Down Modes. Figure 2.13 State Transitions 2.9 2.9.1 Usage Note Usage Notes on Bit-wise Operation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit. The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand. Rev. 3.00 Mar 17, 2006 page 56 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2678 Group has twelve operating modes (modes 1, 2, 4 to 7, and 10 to 15). All operating modes are available for the flash memory version. Modes 1, 2, and 4 to 7 are available in the masked ROM version. Modes 1 and 2 are available in the ROMless version. The H8S/2678R Group has seven operating modes (modes 1 to 7). All operating modes are available for the flash memory version. Modes 1 and 2 are available in the ROMless version. These modes are determined by the mode pin (MD2 to MD0) setting. Modes 1, 2, and 4 to 6 are externally expanded modes in which the CPU can access an external memory and peripheral devices. In the externally expanded mode, each area can be switched to 8bit or 16-bit address space by the bus controller. If one of areas is set to 16-bit address space, the bus mode is 16 bits. If all areas are set to 8-bit address space, the bus mode is 8 bits. Mode 7 is a single-chip activation externally expanded mode in which the CPU can switch to access an external memory and peripheral devices at the beginning of a program execution. Modes 3, 10, and 11 are boot modes in which the flash memory can be accessed. Modes 12 to 15 are user program modes in which the flash memory can be accessed. For details, refer to section 19, Flash Memory (F-ZTAT Version). Do not change the FWE and MD2 to MD0 pin settings during operation. Rev. 3.00 Mar 17, 2006 page 57 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection External Data Bus Description Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM disabled Boot mode Expanded mode with on-chip ROM enabled Expanded mode with on-chip ROM enabled Expanded mode with on-chip ROM enabled Single-chip mode Boot mode Boot mode User program mode User program mode User program mode User program mode On-Chip ROM Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Initial Width 16 bits 8 bits -- 8 bits 16 bits 8 bits -- 8 bits -- 8 bits 16 bits 8 bits -- Max. Value 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits MCU Operating Mode*1 FWE*2 MD2 MD1 1 2 3 4 5 6 7 10 11 12 13 14 15 0 0 -- 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 CPU Operating MD0 Mode 1 0 1 0 1 0 1 0 1 0 1 0 1 Advanced Advanced Advanced Advanced Advanced Advanced Advanced Advanced Advanced Advanced Advanced Advanced Advanced Notes: 1. Modes 1, 2, 4 to 7, and 10 to 15 are supported in the H8S/2678 Group. Modes 1 to 7 are supported in the H8S/2678R Group. 2. The FWE pin setting is available only in the H8S/2678 Group. The FWE pin is not available in the H8S/2678R Group. 3.2 Register Descriptions The following registers are related to the operating mode. * Mode control register (MDCR) * System control register (SYSCR) Rev. 3.00 Mar 17, 2006 page 58 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of the H8S/2678 Group chip. Bit 7 to 3 2 1 0 Bit Name -- Initial Value All 0 R/W -- Descriptions Reserved These bits are always read as 0 and cannot be modified. MDS2 MDS1 MDS0 --* --* --* R R R Mode Select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits and they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * Determined by pins MD2 to MD0. 3.2.2 System Control Register (SYSCR) SYSCR selects saturating or non-saturating calculation for the MAC instruction, controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), sets external bus mode, and enables or disables on-chip RAM. Bit 7, 6 5 Bit Name -- MACS Initial Value All 1 0 R/W R/W R/W Descriptions Reserved The initial value should not be modified. MAC Saturation Selects either saturating or non-saturating calculation for the MAC instruction. 0: Non-saturating calculation for MAC instruction 1: Saturating calculation for MAC instruction 4 -- 0 R/W Reserved The initial value should not be modified. Rev. 3.00 Mar 17, 2006 page 59 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes Bit 3 Bit Name FLSHE Initial Value 0 R/W R/W Descriptions Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). If this bit is set to 1, the flash memory control registers can be read/written to. If this bit is cleared to 0, the flash memory control registers are not selected. At this time, the contents of the flash memory control registers are maintained. This bit should be written to 0 other than flash memory version. 0: Flash memory control registers are not selected for area H'FFFFC8 to H'FFFFCB 1: Flash memory control registers are selected for area H'FFFFC8 to H'FFFFCB 2 1 -- EXPE 0 -- -- R/W Reserved This bit is always read as 0 and cannot be modified. External Bus Mode Enable Sets external bus mode. In modes 1, 2, and 4 to 6, this bit is fixed at 1 and cannot be modified. In mode 3* and 7, this bit has an initial value of 0, and can be read and written. Writing of 0 to EXPE when its value is 1 should only be carried out when an external bus cycle is not being executed. 0: External bus disabled 1: External bus enabled 0 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Note: * Mode 3 is available only in the F-ZTAT version of H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 60 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 3.3.2 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for all areas by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. 3.3.3 Mode 3 This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for accessing to the flash memory. Mode 3 is available only in the flash memory version of the H8S/2678R Group. 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports A to C function as input ports immediately after a reset, but can be set to function as an address bus. For details, see section 10, I/O Ports. Ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any area by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. In the flash memory version, user program mode is entered by setting 1 to the SWE bit of FLMCR1. Rev. 3.00 Mar 17, 2006 page 61 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes 3.3.5 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in an external ROM connected to the first half of area 0 is executed. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for any area by the bus controller, the bus mode switches to 8 bits. In the flash memory version, user program mode is entered by setting 1 to the SWE bit of FLMCR1. 3.3.6 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in an external ROM connected to the first half of area 0 is executed. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H carry bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access is designated for any area by the bus controller, the bus mode switches to 16 bits and port E functions as a data bus. In the flash memory version, user program mode is entered by setting 1 to the SWE bit of FLMCR1. 3.3.7 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, and the chip starts up in single-chip mode. External addresses cannot be used in single-chip mode. The initial mode after a reset is single-chip mode, with all I/O ports available for use as input/output ports. However, the mode can be switched to externally expanded mode by setting 1 to the EXPE bit of SYSCR and then the external address space is enabled. When externally expanded mode is selected, all areas are initially designated as 16-bit access space. The function of pins in ports A to H is the same as in externally expanded mode with on-chip ROM enabled. In the flash memory version, user program mode is entered by setting 1 to the SWE bit of FLMCR1. Rev. 3.00 Mar 17, 2006 page 62 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes 3.3.8 Mode 10 This is flash memory boot mode. This mode is the same as mode 4, except for accessing to the flash memory. Mode 10 is available only in the flash memory version of the H8S/2678 Group. 3.3.9 Mode 11 This is flash memory boot mode. This mode is the same as mode 7, except for accessing to the flash memory. Mode 11 is available only in the flash memory version of the H8S/2678 Group. 3.3.10 Mode 12 This is flash memory user program mode. This mode is the same as mode 4, except for accessing to the flash memory. Mode 12 is available only in the flash memory version of the H8S/2678 Group. 3.3.11 Mode 13 This is flash memory user program mode. This mode is the same as mode 5, except for accessing to the flash memory. Mode 13 is available only in the flash memory version of the H8S/2678 Group. 3.3.12 Mode 14 This is flash memory user program mode. This mode is the same as mode 6, except for accessing to the flash memory. Mode 14 is available only in the flash memory version of the H8S/2678 Group. 3.3.13 Mode 15 This is flash memory user program mode. This mode is the same as mode 7, except for accessing to the flash memory. Mode 15 is available only in the flash memory version of the H8S/2678 Group. 3.3.14 Pin Functions The pin functions of ports A to H are switched according to operating mode. Table 3.2 shows the pin functions in each operating mode. Rev. 3.00 Mar 17, 2006 page 63 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes Table 3.2 Port Port A Pin Functions in Each Operating Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode Mode 1 2 3 4 5 6 7 10 11 12 13 14 15 PA7 to PA5 PA4 to PA0 P*/A A A P*/A P*/A A A P*/A P*/A P*/A A P*/A A P*/A P*/A A A P*/A P*/A P*/A P*/A P*/A A P*/A P*/A A Port B Port C Port D Port E Port F PF7, PF6 PF5, PF4 PF3 PF2 to PF0 Port G PG6 to PG1 PG0 Port H P*/A P*/A P*/A A A P*/A A A A A P*/A P*/A P*/A P*/A A A P*/A D D D D P*/D D P*/D D D D P*/D * P*/D P*/D P*/D P/D* P*/D P*/D P*/D P*/D P*/D P/D* P*/D P*/D P/D P/C* P*/C P*/C P/C* P/C* P/C* P*/C P*/C P*/C P/C* P/C* P/C* P*/C C C C C C C P/C* P*/C C C C P*/A P*/A P*/D P*/D P/C* P/C* P*/C P*/C P/C* P/C* P/C* P*/C P*/C P*/C P/C* P/C* P/C* P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P/C* P/C* P*/C P/C* P/C* P/C* P*/C P/C* P/C* P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C Legend: P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output Notes: Modes 1, 2, 4 to 7, 10 to 15 are supported in H8S/2678 Group. Modes 1 to 7 are supported in H8S/2678R Group. * After reset Rev. 3.00 Mar 17, 2006 page 64 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.6 show memory maps for each product. ROM: 256 kbytes RAM: 8 kbytes Mode 4 (expanded mode with on-chip ROM enabled) H'000000 RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 On-chip ROM H'040000 External address space External address space H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.1 H8S/2676 Memory Map (1) Rev. 3.00 Mar 17, 2006 page 65 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Mode 7 (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM External address space H'040000 H'100000 External address space/reserved area*2 On-chip ROM H'140000 External address space H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF External address space/reserved area*2 Internal I/O registers External address space/reserved area*2 H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Internal I/O registers Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. 2. When EXPE = 1, external address space; when EXPE = 0, reserved area. 3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1. When EXPE = 0, on-chip RAM area. Figure 3.1 H8S/2676 Memory Map (2) Rev. 3.00 Mar 17, 2006 page 66 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Mode 10 Boot mode (expanded mode with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Mode 11 Boot mode (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM On-chip ROM H'040000 H'040000 External address space External address space/reserved area*1 H'FFA000 H'FFA000 On-chip RAM*2 H'FFC000 External address space H'FFFC00 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF On-chip RAM*2 External address space/reserved area*1 Internal I/O registers Internal I/O registers External address space/reserved area*1 H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Internal I/O registers Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area. 2. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Figure 3.1 H8S/2676 Memory Map (3) Rev. 3.00 Mar 17, 2006 page 67 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 8 kbytes Mode 12 User program mode (expanded mode with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Modes 13 and 14 User program mode (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 8 kbytes Mode 15 User program mode (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM On-chip ROM H'040000 External address space H'040000 H'100000 External address space External address space/reserved area*1 On-chip ROM H'140000 External address space H'FFA000 H'FFA000 On-chip RAM*2 On-chip RAM*2 H'FFA000 On-chip RAM*2 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF External address space/reserved area*1 H'FFC000 External address space H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF H'FFC000 External address space H'FFFC00 Internal I/O registers Internal I/O registers External address space Internal I/O registers Internal I/O registers External address space/reserved area*1 H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Internal I/O registers Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area. 2. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Figure 3.1 H8S/2676 Memory Map (4) Rev. 3.00 Mar 17, 2006 page 68 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 ROM: 128 kbytes RAM: 8 kbytes Mode 4 (expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'020000 External address space External address space H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.2 H8S/2675 Memory Map (1) Rev. 3.00 Mar 17, 2006 page 69 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes ROM: 128 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 128 kbytes RAM: 8 kbytes Mode 7 (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'020000 External address space H'100000 External address space/reserved area*2 On-chip ROM H'120000 External address space H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF External address space/reserved area*2 Internal I/O registers External address space/reserved area*2 H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Internal I/O registers Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. 2. When EXPE = 1, external address space; when EXPE = 0, reserved area. 3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1. When EXPE = 0, on-chip RAM area. Figure 3.2 H8S/2675 Memory Map (2) Rev. 3.00 Mar 17, 2006 page 70 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 4 (expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 External address space External address space H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.3 H8S/2673 Memory Map (1) Rev. 3.00 Mar 17, 2006 page 71 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes ROM: 64 kbytes RAM: 8 kbytes Modes 5 and 6 (external ROM activation expanded modes with on-chip ROM enabled) H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 7 (single-chip activation expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 External address space H'100000 External address space/reserved area*2 On-chip ROM H'110000 External address space H'FFA000 On-chip RAM/external address space*1 H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFA000 On-chip RAM/external address space*3 H'FFC000 H'FFFC00 H'FFFF00 H'FFFF20 H'FFFFFF External address space/reserved area*2 Internal I/O registers External address space/reserved area*2 H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Internal I/O registers Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. 2. When EXPE = 1, external address space; when EXPE = 0, reserved area. 3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1. When EXPE = 0, on-chip RAM area. Figure 3.3 H8S/2673 Memory Map (2) Rev. 3.00 Mar 17, 2006 page 72 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes RAM: 8 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.4 H8S/2670 Memory Map Rev. 3.00 Mar 17, 2006 page 73 of 926 REJ09B0283-0300 Section 3 MCU Operating Modes RAM: 32 kbytes Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FF4000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0. Figure 3.5 H8S/2674R Memory Map Rev. 3.00 Mar 17, 2006 page 74 of 926 REJ09B0283-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1. Starts when the direct transition occurs by execution of the SLEEP instruction. Starts when execution of the current instruction or exception 3 handling ends, if an interrupt request has been issued.* 4 1 Trace* 2 Direct transition* Interrupt Low Trap instruction* Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Not available in this LSI. 3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 4. Trap instruction exception handling requests are accepted at all times in program execution state. 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Rev. 3.00 Mar 17, 2006 page 75 of 926 REJ09B0283-0300 Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Vector Address* 1 Exception Source Power-on reset 2 Manual reset * Reserved for system use Vector Number 0 1 2 3 4 Normal Mode* 2 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0019 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 Trace Interrupt (direct transition)* Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use 2 5 6 7 8 9 10 11 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 16 17 18 19 20 21 22 23 24 25 26 27 28 Rev. 3.00 Mar 17, 2006 page 76 of 926 REJ09B0283-0300 Section 4 Exception Handling Vector Address* Exception Source External interrupt IRQ13 IRQ14 IRQ15 Internal interrupt* 3 1 Vector Number 29 30 31 32 99 Normal Mode* 2 Advanced Mode H'0074 to H'0077 H'0078 to H'007B H'007C to H'007F H'0080 to H'0083 H'018C to H'018F H'003A to H'003B H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'00C6 to H'00C7 Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details see section 14, Watchdog Timer. The interrupt control mode is 0 immediately after reset. 4.3.1 Reset exception handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence. Rev. 3.00 Mar 17, 2006 page 77 of 926 REJ09B0283-0300 Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) Rev. 3.00 Mar 17, 2006 page 78 of 926 REJ09B0283-0300 Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction * * * RES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled) 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Functions after Reset Release After reset release, MSTPCR is initialized to H'0FFF and all modules except the DMAC, EXDMAC and the DTC enter module stop mode. Rev. 3.00 Mar 17, 2006 page 79 of 926 REJ09B0283-0300 Section 4 Exception Handling Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR I UI I2 to I0 EXR T Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. Trace exception handling cannot be used. 1 -- -- 0 4.5 Interrupts Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. Rev. 3.00 Mar 17, 2006 page 80 of 926 REJ09B0283-0300 Section 4 Exception Handling The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. Rev. 3.00 Mar 17, 2006 page 81 of 926 REJ09B0283-0300 Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR*1 PC (16 bits) CCR CCR*1 PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Notes: 1. Ignored on return. 2. Normal modes are not available in this LSI. Interrupt control mode 2 Figure 4.3 Stack Status after Exception Handling Rev. 3.00 Mar 17, 2006 page 82 of 926 REJ09B0283-0300 Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation when the SP value is odd. Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAP instruction executed SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L Stack pointer SP: MOV.B R1L, @-ER7 Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd Rev. 3.00 Mar 17, 2006 page 83 of 926 REJ09B0283-0300 Section 4 Exception Handling Rev. 3.00 Mar 17, 2006 page 84 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seventeen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ15 to IRQ0. * DTC and DMAC control DTC and DMAC activations are performed by means of interrupts. Rev. 3.00 Mar 17, 2006 page 85 of 926 REJ09B0283-0300 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR SSIER ITSR ISCR IER Internal interrupt sources SWDTEND to TEI IPR Interrupt controller Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register IPR: Interrupt priority register INTCR: Interrupt control register ITSR: IRQ pin select register SSIER: Software standby release IRQ enable register Priority determination I I2 to I0 Interrupt request Vector number CPU CCR EXR Figure 5.1 Block Diagram of Interrupt Controller Rev. 3.00 Mar 17, 2006 page 86 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Name NMI IRQ15 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable external interrupt Rising or falling edge can be selected. Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers. * Interrupt control register (INTCR) * IRQ sense control register H (ISCRH) * IRQ sense control register L (ISCRL) * IRQ enable register (IER) * IRQ status register (ISR) * IRQ pin select register (ITSR) * Software standby release IRQ enable register (SSIER) * Interrupt priority register A (IPRA) * Interrupt priority register B (IPRB) * Interrupt priority register C (IPRC) * Interrupt priority register D (IPRD) * Interrupt priority register E (IPRE) * Interrupt priority register F (IPRF) * Interrupt priority register G (IPRG) * Interrupt priority register H (IPRH) * Interrupt priority register I (IPRI) * Interrupt priority register J (IPRJ) * Interrupt priority register K (IPRK) Rev. 3.00 Mar 17, 2006 page 87 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7, 6 Bit Name -- Initial Value All 0 R/W R/W Description Reserved These bits can be read from or written to. However, the write value should always be 0. 5 4 INTM1 INTM0 0 0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0, and IPR. 11: Setting prohibited. 3 NMIEG 0 R/W NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input 2 to 0 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt. IPR should be read in word size. Rev. 3.00 Mar 17, 2006 page 88 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 15 Bit Name -- Initial Value 0 R/W -- Description Reserved This bit is always read as 0 and cannot be modified. 14 13 12 IPR14 IPR13 IPR12 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 11 -- 0 -- Reserved This bit is always read as 0 and cannot be modified. 10 9 8 IPR10 IPR9 IPR8 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 7 -- 0 -- Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 89 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 6 5 4 Bit Name IPR6 IPR5 IPR4 Initial Value 1 1 1 R/W R/W R/W R/W Description Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 -- 0 -- Reserved This bit is always read as 0 and cannot be modified. 2 1 0 IPR2 IPR1 IPR0 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 3.00 Mar 17, 2006 page 90 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit 15 Bit Name IRQ15E Initial Value 0 R/W R/W Description IRQ15 Enable The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable The IRQ13 interrupt request is enabled when this bit is 1. 12 IRQ12E 0 R/W IRQ12 Enable The IRQ12 interrupt request is enabled when this bit is 1. 11 IRQ11E 0 R/W IRQ11 Enable The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. 8 IRQ8E 0 R/W IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. 7 IRQ7E 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. Rev. 3.00 Mar 17, 2006 page 91 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 5 Bit Name IRQ5E Initial Value 0 R/W R/W Description IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0. * ISCRH Bit 15 14 Bit Name IRQ15SCB IRQ15SCA Initial Value 0 0 R/W R/W R/W Description IRQ15 Sense Control B IRQ15 Sense Control A 00: Interrupt request generated at IRQ15 input low level 01: Interrupt request generated at falling edge of IRQ15 input 10: Interrupt request generated at rising edge of IRQ15 input 11: Interrupt request generated at both falling and rising edges of IRQ15 input Rev. 3.00 Mar 17, 2006 page 92 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 13 12 Bit Name IRQ14SCB IRQ14SCA Initial Value 0 0 R/W R/W R/W Description IRQ14 Sense Control B IRQ14 Sense Control A 00: Interrupt request generated at IRQ14 input low level 01: Interrupt request generated at falling edge of IRQ14 input 10: Interrupt request generated at rising edge of IRQ14 input 11: Interrupt request generated at both falling and rising edges of IRQ14 input 11 10 IRQ13SCB IRQ13SCA 0 0 R/W R/W IRQ13 Sense Control B IRQ13 Sense Control A 00: Interrupt request generated at IRQ13 input low level 01: Interrupt request generated at falling edge of IRQ13 input 10: Interrupt request generated at rising edge of IRQ13 input 11: Interrupt request generated at both falling and rising edges of IRQ13 input 9 8 IRQ12SCB IRQ12SCA 0 0 R/W R/W IRQ12 Sense Control B IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input Rev. 3.00 Mar 17, 2006 page 93 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 7 6 Bit Name IRQ11SCB IRQ11SCA Initial Value 0 0 R/W R/W R/W Description IRQ11 Sense Control B IRQ11 Sense Control A 00: Interrupt request generated at IRQ11 input low level 01: Interrupt request generated at falling edge of IRQ11 input 10: Interrupt request generated at rising edge of IRQ11 input 11: Interrupt request generated at both falling and rising edges of IRQ11 input 5 4 IRQ10SCB IRQ10SCA 0 0 R/W R/W IRQ10 Sense Control B IRQ10 Sense Control A 00: Interrupt request generated at IRQ10 input low level 01: Interrupt request generated at falling edge of IRQ10 input 10: Interrupt request generated at rising edge of IRQ10 input 11: Interrupt request generated at both falling and rising edges of IRQ10 input 3 2 IRQ9SCB IRQ9SCA 0 0 R/W R/W IRQ9 Sense Control B IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input Rev. 3.00 Mar 17, 2006 page 94 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 1 0 Bit Name IRQ8SCB IRQ8SCA Initial Value 0 0 R/W R/W R/W Description IRQ8 Sense Control B IRQ8 Sense Control A 00: Interrupt request generated at IRQ8 input low level 01: Interrupt request generated at falling edge of IRQ8 input 10: Interrupt request generated at rising edge of IRQ8 input 11: Interrupt request generated at both falling and rising edges of IRQ8 input * ISCRL Bit 15 14 Bit Name IRQ7SCB IRQ7SCA Initial Value 0 0 R/W R/W R/W Description IRQ7 Sense Control B IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 12 IRQ6SCB IRQ6SCA 0 0 R/W R/W IRQ6 Sense Control B IRQ6 Sense Control A 00: Interrupt request generated at IRQ6 input low level 01: Interrupt request generated at falling edge of IRQ6 input 10: Interrupt request generated at rising edge of IRQ6 input 11: Interrupt request generated at both falling and rising edges of IRQ6 input Rev. 3.00 Mar 17, 2006 page 95 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 11 10 Bit Name IRQ5SCB IRQ5SCA Initial Value 0 0 R/W R/W R/W Description IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input low level 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input 9 8 IRQ4SCB IRQ4SCA 0 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 6 IRQ3SCB IRQ3SCA 0 0 R/W R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input low level 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input Rev. 3.00 Mar 17, 2006 page 96 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 5 4 Bit Name IRQ2SCB IRQ2SCA Initial Value 0 0 R/W R/W R/W Description IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input low level 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input 3 2 IRQ1SCB IRQ1SCA 0 0 R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 0 IRQ0SCB IRQ0SCA 0 0 R/W R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input low level 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Rev. 3.00 Mar 17, 2006 page 97 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting condition] When the interrupt source selected by ISCR occurs [Clearing conditions] * * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 (n=15 to 0) Note: * Only 0 can be written, to clear the flag. * * 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. Bit 15 Bit Name ITS15 Initial Value 0 R/W R/W Description Selects IRQ15 input pin. 0: PF2 1: P27 14 ITS14 0 R/W Selects IRQ14 input pin. 0: PF1 1: P26 Rev. 3.00 Mar 17, 2006 page 98 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 13 Bit Name ITS13 Initial Value 0 R/W R/W Description Selects IRQ13 input pin. 0: P65 1: P25 12 ITS12 0 R/W Selects IRQ12 input pin. 0: P64 1: P24 11 ITS11 0 R/W Selects IRQ11 input pin. 0: P63 1: P23 10 ITS10 0 R/W Selects IRQ10 input pin. 0: P62 1: P22 9 ITS9 0 R/W Selects IRQ9 input pin. 0: P61 1: P21 8 ITS8 0 R/W Selects IRQ8 input pin. 0: P60 1: P20 7 ITS7 0 R/W Selects IRQ7 input pin. 0: P57 1: PH3 6 ITS6 0 R/W Selects IRQ6 input pin. 0: P56 1: PH2 5 ITS5 0 R/W Selects IRQ5 input pin. 0: P55 1: P85 4 ITS4 0 R/W Selects IRQ4 input pin. 0: P54 1: P84 Rev. 3.00 Mar 17, 2006 page 99 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Bit 3 Bit Name ITS3 Initial Value 0 R/W R/W Description Selects IRQ3 input pin. 0: P53 1: P83 2 ITS2 0 R/W Selects IRQ2 input pin. 0: P52 1: P82 1 ITS1 0 R/W Selects IRQ1 input pin. 0: P51 1: P81 0 ITS0 0 R/W Selects IRQ0 input pin. 0: P50 1: P80 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Software Standby Release IRQ Setting These bits select the IRQn pins used to recover from the software standby state. 0: IRQn requests are not sampled in the software standby state (Initial value when n = 15 to 3) 1: When an IRQn request occurs in the software standby state, the chip recovers from the software standby state after the elapse of the oscillation settling time (Initial value when n = 2 to 0) (n = 15 to 0) Rev. 3.00 Mar 17, 2006 page 100 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to restore the chip from software standby mode. NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0. Interrupts IRQ15 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ15 to IRQ0. * Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. When IRQ15 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in the interrupt handling routine and clear the IRQnF bit (n = 0 to 15) in ISR to 0. Interrupts may not be executed when the corresponding IRQ is set to high before the interrupt handling starts. Detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2. Rev. 3.00 Mar 17, 2006 page 101 of 926 REJ09B0283-0300 Section 5 Interrupt Controller IRQnSCA, IRQnSCB IRQnF Edge/ level detection circuit S R Clear signal Note: n = 15 to 0 IRQnE Q IRQn interrupt request IRQn input Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. * When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit. 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Rev. 3.00 Mar 17, 2006 page 102 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Vector Number 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C Low IPRF10 to IPRF8 -- -- IPR -- IPRA14 to IPRA12 IPRA10 to IPRA8 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB14 to IPRB12 IPRB10 to IPRB8 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC14 to IPRC12 IPRC10 to IPRC8 IPRC6 to IPRC4 IPRC2 to IPRC0 IPRD14 to IPRD12 IPRD10 to IPRD8 IPRD6 to IPRD4 IPRD2 to IPRD0 IPRE14 to IPRE12 IPRE10 to IPRE8 IPRE6 to IPRE4 IPRE2 to IPRE0 IPRF14 to IPRF12 -- -- -- -- -- Priority High DTC DMAC Activation Activation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt Source External pin Origin of Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 DTC WDT -- Refresh controller -- SWDTEND WOVI Reserved for system use CMI Reserved for system use ADI Reserved for system use A/D -- Rev. 3.00 Mar 17, 2006 page 103 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Vector Address* Vector Number 40 41 42 43 44 45 46 47 TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V -- Reserved for system use 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 TPU_4 TGI4A TGI4B TCI4V TCI4U 64 65 66 67 Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C Low -- -- IPRG6 to IPRG4 -- -- -- -- -- -- -- IPRG10 to IPRG8 -- -- -- -- -- -- -- -- -- IPRG14 to IPRG12 -- -- -- -- -- IPRF2 to IPRF0 -- -- -- IPRF6 to IPRF4 -- -- -- -- IPR IPRF6 to IPRF4 Priority High -- -- -- -- -- -- -- DTC DMAC Activation Activation Interrupt Source TPU_0 Origin of Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V -- Reserved for system use Rev. 3.00 Mar 17, 2006 page 104 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Vector Address* Vector Number 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Advanced Mode H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C IPRJ14 to IPRJ12 -- -- -- -- IPRH0 to IPRH0 IPRI14 to IPRI12 IPRI10 to IPRI8 IPRI6 to IPRI4 IPRI2 to IPRI0 -- -- -- -- -- IPRH6 to IPRH4 -- -- IPRH10 to IPRH8 -- -- IPRH14 to IPRH12 -- -- IPR IPRG2 to IPRG0 Priority High -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DTC DMAC Activation Activation Interrupt Source TPU_5 Origin of Interrupt Source TGI5A TGI5B TCI5V TCI5U TMR_0 CMIA0 CMIB0 OVI0 -- TMR_1 Reserved for system use CMIA1 CMIB1 OVI1 -- DMAC Reserved for system use DMTEND0A DMTEND0B DMTEND1A DMTEND1B EXDMAC EXDMTEND0 EXDMTEND1 EXDMTEND2 EXDMTEND3 SCI_0 ERI0 RXI0 TXI0 TEI0 SCI_1 ERI1 RXI1 TXI1 TEI1 Low -- -- Rev. 3.00 Mar 17, 2006 page 105 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Vector Address* Vector Number 96 97 98 99 100 101 102 103 -- Reserved for system use 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Advanced Mode H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC H'01D0 H'01D4 H'01D8 H'01DC Low IPRK6 to IPRK4 IPRK10 to IPRK8 IPRK14 to IPRK12 IPRJ2 to IPRJ0 IPRJ6 to IPRJ4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IPR IPRJ10 to IPRJ8 Priority High DTC DMAC Activation Activation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt Source SCI_2 Origin of Interrupt Source ERI2 RXI2 TXI2 TEI2 -- Reserved for system use Rev. 3.00 Mar 17, 2006 page 106 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Vector Address* Vector Number 120 121 122 123 124 125 126 127 Advanced Mode H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01EC Low IPR IPRK2 to IPRK0 Priority High DTC DMAC Activation Activation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt Source -- Origin of Interrupt Source Reserved for system use Note: * Lower 16 bits of the start address. 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Priority Setting Registers Default Interrupt Mask Bits Description I The priorities of interrupt sources are fixed at the default settings. Interrupt sources except for NMI is masked by the I bit. 8 priority levels except for NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0. Interrupt Control Mode 0 2 IPR I2 to I0 Rev. 3.00 Mar 17, 2006 page 107 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 3.00 Mar 17, 2006 page 108 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes No NMI No I=0 Yes No Hold pending No IRQ0 Yes No IRQ1 Yes TEI_2 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.00 Mar 17, 2006 page 109 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 3.00 Mar 17, 2006 page 110 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes No Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 3.00 Mar 17, 2006 page 111 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 3.00 Mar 17, 2006 page 112 of 926 REJ09B0283-0300 Interrupt acceptance Internal operation stack Vector fetch Internal operation Interrupt level determination Instruction Wait for end of instruction prefetch Interrupt handling routine instruction prefetch Interrupt request signal Internal address bus (1) (3) (5) (7) (9) (11) (13) Internal read signal Internal write signal (2) (4) (6) (8) (10) (12) (14) Figure 5.5 Interrupt Exception Handling (6) (8) (9) (11) (10) (12) (13) (14) Internal data bus Rev. 3.00 Mar 17, 2006 page 113 of 926 REJ09B0283-0300 Section 5 Interrupt Controller (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times Normal Mode* Interrupt control mode 0 1 5 Advanced Mode Interrupt control mode 0 3 Interrupt control mode 2 3 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* Interrupt control mode 2 3 3 Number of wait states until executing 1 to 19 +2*SI 1 to 19+2*SI 2 instruction ends* PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 Internal processing* 1 to 19+2*SI 1 to 19+2*SI 2*SK 2*SI 2*SI 2 12 to 32 3*SK 2*SI 2*SI 2 13 to 33 2*SK SI 2*SI 2 11 to 31 3*SK SI 2*SI 2 12 to 32 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI. Rev. 3.00 Mar 17, 2006 page 114 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6+2m Legend: m: Number of wait states in an external device access 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Activation request to DMAC * Selection of a number of the above For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC). Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller. Rev. 3.00 Mar 17, 2006 page 115 of 926 REJ09B0283-0300 Section 5 Interrupt Controller DMAC Clear signal Interrupt request IRQ interrupt Interrupt source clear signal Disable signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5.6 DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Source: The activation factors for each channel of DMAC are selected by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation factors are managed by DMAC. By setting the DTA bit to 1, the interrupt factor which were the activation factor for that DMAC do not act as the DTC activation factor or the CPU interrupt factor. Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation source or CPU interrupt source by the DTCE bit of DTCERA to DTCERF of DTC. By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after DTC data transfer, and request a CPU interrupt. If DTC carries out the designate number of data transfers and the transfer counter reads 0, after DTC data transfer, the DTCE bit is also cleared to 0, and an interrupt is requested to the CPU. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See table 9.1 for the respective priority. DMAC inputs activation factor directly to each channel. Rev. 3.00 Mar 17, 2006 page 116 of 926 REJ09B0283-0300 Section 5 Interrupt Controller (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or CPU interrupt factor, these operate independently. Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification of the DTA bit of DMAC's DMABCR, the DTCE bit of DTC's DTCERA to DTCERH, and the DISEL bit of DTC's MRB. Table 5.6 Interrupt Source Selection and Clearing Control Settings DMAC DTA 0 DTCE 0 1 1 * DTC DISEL * 0 1 * X X Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant interrupt cannot be used. * : Don't care Note: The SCI or A/D converter interrupt source is cleared when the DMAC or DTC reads or writes to the prescribed register, and is not dependent upon the DTA bit or DISEL bit. Interrupt Sources Selection/Clearing Control DMAC DTC X X CPU 5.7 5.7.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher Rev. 3.00 Mar 17, 2006 page 117 of 926 REJ09B0283-0300 Section 5 Interrupt Controller priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in the TPU's TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.7 Contention between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev. 3.00 Mar 17, 2006 page 118 of 926 REJ09B0283-0300 Section 5 Interrupt Controller 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.7.5 Change of IRQ Pin Select Register (ITSR) Setting When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15) of ISR may be set to 1 at the unintended timing if the selected pin level before the change is different from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 15) is enabled, the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be cleared to 0. 5.7.6 Note on IRQ Status Register (ISR) Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from ISR after a reset and then write 0 to clear the IRQnF flags. Rev. 3.00 Mar 17, 2006 page 119 of 926 REJ09B0283-0300 Section 5 Interrupt Controller Rev. 3.00 Mar 17, 2006 page 120 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus mastership--the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC), and data transfer controller (DTC). 6.1 Features * Manages external address space in area units Manages the external address space divided into eight areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM, DRAM, or synchronous DRAM* interface can be set * Basic bus interface Chip select signals (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set independently for areas 0 and 1 * DRAM interface DRAM interface can be set for areas 2 to 5 * Synchronous DRAM interface Continuous synchronous DRAM space can be set for areas 2 to 5 * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, and DTC Note: * The Synchronous DRAM interface is not supported in the H8S/2678 Group. BSCS202A_010020020400 Rev. 3.00 Mar 17, 2006 page 121 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1. EXDMAC address bus Internal address bus Address selector Area decoder CS7 to CS0 External bus controller WAIT BREQ BACK BREQO Internal bus master bus request signal EXDMAC bus request signal Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal External bus arbiter External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Internal bus arbiter Control registers Internal data bus ABWCR ASTCR DRAMCR DRACCR* REFCR RTCNT CSACRL RTCOR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH BROMCRH BROMCRL BCR Legend: ABWCR ASTCR WTCRAH, WTCRAL, WTCRBH, and WTCRBL RDNCR CSACRH and CSACRL BROMCRH : Bus width control register : Access state control register : Wait control registers AH, AL, BH, and BL : Read strobe timing control register : CS assertion period control registers : Area 0 burst ROM interface control register BROMCRL : Area 1 burst ROM interface control register BCR : Bus control register DRAMCR : DRAM control register DRACCR : DRAM access control register REFCR : Refresh control register RTCNT : Refresh timer counter RTCOR : Refresh time constant register Note: * DRACCR is an 8-bit register in the H8S/2678 Group and a 16-bit register in the H8S/2678R Group. Figure 6.1 Block Diagram of Bus Controller Rev. 3.00 Mar 17, 2006 page 122 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Name Address strobe Pin Configuration Symbol AS I/O Output Function Strobe signal indicating that basic bus interface space is accessed and address output on address bus is enabled. Strobe signal indicating that basic bus interface space is being read. Strobe signal indicating that basic bus interface space is written to, and upper half (D15 to D8) of data bus is enabled or DRAM interface space write enable signal. Strobe signal indicating that basic bus interface space is written to, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected Strobe signal indicating that area 2 is selected, DRAM row address strobe signal when area 2 is DRAM interface space or areas 2 to 5 are set as continuous DRAM interface space, or row address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Strobe signal indicating that area 3 is selected, DRAM row address strobe signal when area 3 is DRAM interface space, or column address strobe signal of the synchronous DRAM when the synchronous DRAM interface is selected. Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM interface space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected. Read High write/write enable RD HWR Output Output Low write LWR Output Chip select 0 Chip select 1 Chip select 2/row address strobe 2/row address strobe* CS0 CS1 CS2/ RAS2/* RAS* Output Output Output Chip select 3/row address strobe 3/column address strobe* CS3/ RAS3/* CAS* Output Chip select 4/row address strobe 4/write enable* CS4/ RAS4/* WE* Output Rev. 3.00 Mar 17, 2006 page 123 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Name Chip select 5/row address strobe 5/SDRAM* Symbol I/O Function Strobe signal indicating that area 5 is selected, DRAM row address strobe signal when area 5 is DRAM interface space, or dedicated clock signal for the synchronous DRAM when the synchronous DRAM interface is selected. Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. 16-bit DRAM interface space upper column address strobe signal, 8-bit DRAM interface space column address strobe signal, upper data mask signal of 16-bit synchronous DRAM interface space, or data mask signal of 8-bit synchronous DRAM interface space. 16-bit DRAM interface space lower column address strobe signal or lower data mask signal for the 16-bit synchronous DRAM interface space. Output enable signal for the DRAM interface space or clock enable signal for the synchronous DRAM interface space. Wait request signal when accessing external space. Request signal for release of bus to external bus master. Acknowledge signal indicating that bus has been released to external bus master. External bus request signal used when internal bus master accesses external address space when external bus is released. Data transfer acknowledge signal for single address transfer by DMAC channel 1. Data transfer acknowledge signal for single address transfer by DMAC channel 0. Data transfer acknowledge signal for single address transfer by EXDMAC channel 3. Data transfer acknowledge signal for single address transfer by EXDMAC channel 2. Output CS5/ RAS5/* SDRAM* Chip select 6 Chip select 7 Upper column address strobe/upper data mask enable CS6 CS7 UCAS/ DQMU* Output Output Output Lower column address strobe/lower data mask enable Output enable/clock enable Wait Bus request Bus request acknowledge Bus request output LCAS/ DQML* Output OE/CKE* Output WAIT BREQ BACK BREQO Input Input Output Output Data transfer acknowledge DACK1 1 (DMAC) Data transfer acknowledge DACK0 0 (DMAC) Data transfer acknowledge EDACK3 3 (EXDMAC) Data transfer acknowledge EDACK2 2 (EXDMAC) Output Output Output Output Rev. 3.00 Mar 17, 2006 page 124 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Name Symbol I/O Output Output Function Data transfer acknowledge signal for single address transfer by EXDMAC channel 1. Data transfer acknowledge signal for single address transfer by EXDMAC channel 0. Data transfer acknowledge EDACK1 1 (EXDMAC) Data transfer acknowledge EDACK0 0 (EXDMAC) Note: * These pins are not supported in the H8S/2678 Group. 6.3 Register Descriptions The bus controller has the following registers. * Bus width control register (ABWCR) * Access state control register (ASTCR) * Wait control register AH (WTCRAH) * Wait control register AL (WTCRAL) * Wait control register BH (WTCRBH) * Wait control register BL (WTCRBL) * Read strobe timing control register (RDNCR) * CS assertion period control register H (CSACRH) * CS assertion period control register L (CSACRL) * Area 0 burst ROM interface control register (BROMCRH) * Area 1 burst ROM interface control register (BROMCRL) * Bus control register (BCR) * DRAM control register (DRAMCR) * DRAM access control register (DRACCR) * Refresh control register (REFCR) * Refresh timer counter (RTCNT) * Refresh time constant register (RTCOR) Rev. 3.00 Mar 17, 2006 page 125 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit 7 6 5 4 3 2 1 0 Note: Bit Name ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 * Initial Value* 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. 0: Area n is designated as 16-bit access space 1: Area n is designated as 8-bit access space (n = 7 to 0) In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is initialized to 0. 6.3.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space. Bit 7 6 5 4 3 2 1 0 Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait state insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait state insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait state insertion in area n access is enabled (n = 7 to 0) Rev. 3.00 Mar 17, 2006 page 126 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. * WTCRAH Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 14 13 12 W72 W71 W70 1 1 1 R/W R/W R/W Area 7 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 7 while AST7 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 127 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 10 9 8 Bit Name W62 W61 W60 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted * WTARAL Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W52 W51 W50 1 1 1 R/W R/W R/W Area 5 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 128 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 2 1 0 Bit Name W42 W41 W40 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted * WTCRBH Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 14 13 12 W32 W31 W30 1 1 1 R/W R/W R/W Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 11 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 129 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 10 9 8 Bit Name W22 W21 W20 Initial Value 1 1 1 R/W R/W R/W R/W Description Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM is connected*. The setting of area 2 is reflected to the setting of areas 2 to 5. A CAS latency can be set regardless of whether or not an ASTCR wait state insertion is enabled. 000: 001: 010: 011: 100: 101: 110: 111: 000: 001: 010: 011: Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 4 program wait states inserted 5 program wait states inserted 6 program wait states inserted 7 program wait states inserted Synchronous DRAM of CAS latency 1 is connected to areas 2 to 5. Synchronous DRAM of CAS latency 2 is connected to areas 2 to 5. Synchronous DRAM of CAS latency 3 is connected to areas 2 to 5. Synchronous DRAM of CAS latency 4 is connected to areas 2 to 5. 1XXX: Setting prohibited. Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group. Legend: x: Don't care. Rev. 3.00 Mar 17, 2006 page 130 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) * WTCRBL Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W12 W11 W10 1 1 1 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted 3 -- 0 R Reserved This bit is always read as 0 and cannot be modified. 2 1 0 W02 W01 W00 1 1 1 R/W R/W R/W Area 0 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 0 while AST0 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted 101: 5 program wait states inserted 110: 6 program wait states inserted 111: 7 program wait states inserted Rev. 3.00 Mar 17, 2006 page 131 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit 7 6 5 4 3 2 1 0 Bit Name RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half-state earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time specifications are also one half-state earlier. 0: In an area n read access, the RD is negated at the end of the read cycle 1: In an area n read access, the RD is negated one half-state before the end of the read cycle (n = 7 to 0) Bus cycle T1 T2 T3 RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) Rev. 3.00 Mar 17, 2006 page 132 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices. * CSACRH Bit 7 6 5 4 3 2 1 0 Bit Name CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS and Address Signal Assertion Period Control 1 These bits specify whether or not the Th cycle is to be inserted (see figure 6.3). When an area for which the CSXHn bit is set to 1 is accessed, a one-state Th cycle, in which only the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Th) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Th) is extended (n = 7 to 0) * CSACRL Bit 7 6 5 4 3 2 1 0 Bit Name CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS and Address Signal Assertion Period Control 2 These bits specify whether or not the Tt cycle shown in figure 6.3 is to be inserted. When an area for which the CSXTn bit is set to 1 is accessed, a one-state Tt cycle, in which only the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In area n basic bus interface access, the CSn and address assertion period (Tt) is not extended 1: In area n basic bus interface access, the CSn and address assertion period (Tt) is extended (n = 7 to 0) Rev. 3.00 Mar 17, 2006 page 133 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 Tt Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev. 3.00 Mar 17, 2006 page 134 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit 7 Bit Name BSRMn Initial Value 0 R/W R/W Description Burst ROM Interface Select Selects the basic bus interface or burst ROM interface. 0: Basic bus interface space 1: Burst ROM interface space 6 5 4 BSTSn2 BSTSn1 BSTSn0 0 0 0 R/W R/W R/W Burst Cycle Select These bits select the number of burst cycle states. 000: 1 state 001: 2 states 010: 3 states 011: 4 states 100: 5 states 101: 6 states 110: 7 states 111: 8 states 3, 2 -- All 0 R/W Reserved These bits are always read as 0. The initial value should not be changed. 1 0 BSWDn1 BSWDn0 0 0 R/W R/W Burst Word Number Select These bits select the number of words that can be burst-accessed on the burst ROM interface. 00: Maximum 4 words 01: Maximum 8 words 10: Maximum 16 words 11: Maximum 32 words (n = 1 or 0) Rev. 3.00 Mar 17, 2006 page 135 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit 15 Bit Name BRLE Initial Value 0 R/W R/W Description External Bus Release Enable Enables or disables external bus release. 0: External bus release disabled BREQ, BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled 14 BREQOE 0 R/W BREQO Pin Enable Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state, when an internal bus master performs an external address space access, or when a refresh request is generated. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled 13 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 12 IDLC 1 R/W Idle Cycle State Number Select Specifies the number of states in the idle cycle set by ICIS2 to ICIS0. 0: Idle cycle comprises 1 state 1: Idle cycle comprises 2 states 11 ICIS1 1 R/W Idle Cycle Insert 1 When consecutive external read cycles are performed in different areas, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted Rev. 3.00 Mar 17, 2006 page 136 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 10 Bit Name ICIS0 Initial Value 1 R/W R/W Description Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle. 0: Write data buffer function not used 1: Write data buffer function used 8 WAITE 0 R/W WAIT Pin Enable Selects enabling or disabling of wait input by the WAIT pin. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled 7 to 3 2 -- 0 R/W Reserved These are readable/writable bits, but the write value should always be 0. ICIS2 0 R/W Idle Cycle Insert 2 When an external write cycle and external read cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted Note: Bit 2 is a reserved bit in the H8S/2678 Group. This bit is readable/writable, but the write value should always be 0. 1, 0 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 137 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM* interface settings. Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group. Bit 15 Bit Name OEE Initial Value 0 R/W R/W Description OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space. When the synchronous DRAM is connected, the CKE signal can be output from the (OE) pin. The CKE signal is common to the continuous synchronous DRAM space. 0: OE/CKE signal output disabled (OE)/(CKE) pin can be used as I/O port 1: OE/CKE signal output enabled 14 RAST 0 R/W RAS Assertion Timing Select Selects whether, in DRAM access, the RAS signal is asserted from the start of the Tr cycle (rising edge of ) or from the falling edge of . Figure 6.4 shows the relationship between the RAST bit setting and the RAS assertion timing. The setting of this bit applies to all areas designated as DRAM space. 0: RAS is asserted from falling edge in Tr cycle 1: RAS is asserted from start of Tr cycle 13 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 138 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 12 Bit Name CAST Initial Value 0 R/W R/W Description Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: 2 states 1: 3 states 11 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 10 9 8 RMTS2 RMTS1 RMTS0 0 0 0 R/W R/W R/W DRAM/Continuous Synchronous DRAM Space Select These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin. When continuous synchronous DRAM space is set, it is possible to connect large-capacity synchronous DRAM exceeding 2 Mbytes per area. In this case, the RAS, CAS, and WE signals are output from CS2, CS3, and CS4 pins, respectively. When synchronous DRAM mode is set, the mode registers of the synchronous DRAM can be set. 000: Normal space 001: Normal space in areas 3 to 5 DRAM space in area 2 010: Normal space in areas 4 and 5 DRAM space in areas 2 and 3 011: DRAM space in areas 2 to 5 100: Continuous synchronous DRAM space (setting prohibited in the H8S/2678 Group) 101: Synchronous DRAM mode setting (setting prohibited in the H8S/2678 Group) 110: Setting prohibited 111: Continuous DRAM space in areas 2 to 5 Rev. 3.00 Mar 17, 2006 page 139 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 7 Bit Name BE Initial Value 0 R/W R/W Description Burst Access Enable Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the OE signal must be connected. 0: Full access 1: Access in fast page mode 6 RCDM 0 R/W RAS Down Mode When access to DRAM space is interrupted by an access to normal bus space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1. If this bit is cleared to 0 when set to 1 in the RAS down state, the RAS down state is cleared at that point, and RAS goes high. When continuous synchronous DRAM space is set, reading from and writing to this bit is enabled. However, the setting does not affect the operation. 0: RAS up mode selected for DRAM space access 1: RAS down mode selected for DRAM space access Rev. 3.00 Mar 17, 2006 page 140 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 5 Bit Name DDS Initial Value 0 R/W R/W Description DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM interface. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or DMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled 4 EDDS 0 R/W EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM interface. When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, EXDMAC single address transfer is performed in full access mode regardless of the setting of this bit. This bit has no effect on other bus master external accesses or EXDMAC dual address transfers. 0: Full access is always executed 1: Burst access is enabled 3 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 141 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 2 1 0 Bit Name MXC2 MXC1 MXC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Address Multiplex Select These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison. When the MXC2 bit is set to 1 while continuous synchronous DRAM space is set, the address precharge setting command (Precharge-sel) is output to the upper column address. For details, refer to sections 6.6.2 and 6.7.2, Address Multiplexing. DRAM interface 000: 8-bit shift * When 8-bit access space is designated: Row address bits A23 to A8 used for comparison * When 16-bit access space is designated: Row address bits A23 to A9 used for comparison 001: 9-bit shift * When 8-bit access space is designated: Row address bits A23 to A9 used for comparison * When 16-bit access space is designated: Row address bits A23 to A10 used for comparison 010: 10-bit shift * When 8-bit access space is designated: Row address bits A23 to A10 used for comparison * When 16-bit access space is designated: Row address bits A23 to A11 used for comparison Rev. 3.00 Mar 17, 2006 page 142 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 011: 11-bit shift * When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift * When 8-bit access space is designated: Row address bits A23 to A8 used for comparison * When 16-bit access space is designated: Row address bits A23 to A9 used for comparison The precharge-sel is A15 to A9 of the column address. 101: 9-bit shift * When 8-bit access space is designated: Row address bits A23 to A9 used for comparison * When 16-bit access space is designated: Row address bits A23 to A10 used for comparison The precharge-sel is A15 to A10 of the column address. 110: 10-bit shift * When 8-bit access space is designated: Row address bits A23 to A10 used for comparison * When 16-bit access space is designated: Row address bits A23 to A11 used for comparison The precharge-sel is A15 to A11 of the column address. Rev. 3.00 Mar 17, 2006 page 143 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 111: 11-bit shift * When 8-bit access space is designated: Row address bits A23 to A11 used for comparison * When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address. Bus cycle Tp Tr Tc1 Tc2 Address RAST = 0 RAS RAST = 1 RAS Row address Column address UCAS, LCAS Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) 6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 144 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) * H8S/2678 Group Bit 7 Bit Name DRMI Initial Value 0 R/W R/W Description Idle Cycle Insertion An idle cycle can be inserted after a DRAM read cycle when a continuous normal space access cycle follows a DRAM read cycle. Idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits ICIS1, ICIS0, and IDLC in BCR register 0: Idle cycle not inserted 1: Idle cycle inserted 6 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 5 4 TPC1 TPC0 0 0 R/W R/W Precharge State Control These bits select the number of states in the RAS precharge cycle in normal access and refreshing. 00: 1 state 01: 2 states 10: 3 states 11: 4 states 3, 2 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 1 0 RCD1 RCD0 0 0 R/W R/W RAS-CAS Wait Control These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted Rev. 3.00 Mar 17, 2006 page 145 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) * H8S/2678R Group Bit 15 Bit Name DRMI Initial Value 0 R/W R/W Description Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle. Idle cycle insertion conditions, setting of number of states, etc., comply with settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR register 0: Idle cycle not inserted 1: Idle cycle inserted 14 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 13 12 TPC1 TPC0 0 0 R/W R/W Precharge State Control These bits select the number of states in the RAS precharge cycle in normal access and refreshing. 00: 1 state 01: 2 states 10: 3 states 11: 4 states 11 SDWCD 0 R/W CAS Latency Control Cycle Disabled during Continuous Synchronous DRAM Space Write Access Disables CAS latency control cycle (Tc1) inserted by WTCR settings during synchronous DRAM write access (see figure 6.5). 0: Enables CAS latency control cycle 1: Disables CAS latency control cycle 10 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 146 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 9 8 Bit Name RCD1 RCD0 Initial Value 0 0 R/W R/W R/W Description RAS-CAS Wait Control These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted 7 to 4 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 3 CKSPE 0 R/W Clock Suspend Enable Enables clock suspend mode for extend read data during DMAC and EXDMAC single address transfer with the synchronous DRAM interface. 0: Disables clock suspend mode 1: Enables clock suspend mode 2 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 1 0 RDXC1 RDXC0 0 0 R/W R/W Read Data Extension Cycle Number Selection Selects the number of read data extension cycle (Tsp) insertion state in clock suspend mode. These bits are valid when the CKSPE bit is set to 1. 00: Inserts 1state 01: Inserts 2state 10: Inserts 3state 11: Inserts 4state Rev. 3.00 Mar 17, 2006 page 147 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 Address bus Column address Row address Column address Precharge-sel Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus PALL Tp ACTV Tr NOP Tc1 WRIT Tc2 NOP Address bus Column address Row address Column address Precharge-sel Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 148 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported in the H8S/2678 Group. Bit 15 Bit Name CMF Initial Value 0 R/W R/(W)* Description Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR. [Clearing conditions] * * When 0 is written to CMF after reading CMF = 1 while the RFSHE bit is cleared to 0 When CBR refreshing is executed while the RFSHE bit is set to 1 [Setting condition] When RTCOR = RTCNT 14 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag is set to 1. This bit is valid when refresh control is not performed. When the refresh control is performed, this bit is always cleared to 0 and cannot be modified. 0: Interrupt request by CMF flag disabled 1: Interrupt request by CMF flag enabled 13 12 RCW1 RCW0 0 0 R/W R/W CAS-RAS Wait Control These bits select the number of wait cycles to be inserted between the CAS assert cycle and RAS assert cycle in a DRAM/synchronous DRAM refresh cycle. 00: Wait state not inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Mar 17, 2006 page 149 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 11 Bit Name -- Initial Value 0 R/W R/W Description Reserved This bit can be read from or written to. However, the write value should always be 0. 10 9 8 RTCK2 RTCK1 RTCK0 0 0 0 R/W R/W R/W Refresh Counter Clock Select These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up. 000: Count operation halted 001: Count on /2 010: Count on /8 011: Count on /32 100: Count on /128 101: Count on /512 110: Count on /2048 111: Count on /4096 7 RFSHE 0 R/W Refresh Control Refresh control can be performed. When refresh control is not performed, the refresh timer can be used as an interval timer. 0: Refresh control is not performed 1: Refresh control is performed 6 CBRM 0 R/W CBR Refresh Control Selects CBR refreshing performed in parallel with other external accesses, or execution of CBR refreshing alone. When the continuous synchronous DRAM space is set, this bit can be read/written, but the setting contents do not affect operations. 0: External access during CAS-before-RAS refreshing is enabled 1: External access during CAS-before-RAS refreshing is disabled Rev. 3.00 Mar 17, 2006 page 150 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bit 5 4 Bit Name RLW1 RLW0 Initial Value 0 0 R/W R/W R/W Description Refresh Cycle Wait Control These bits select the number of wait states to be inserted in a DRAM interface CAS-beforeRAS refresh cycle/synchronous DRAM interface auto-refresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space. 00: No wait state inserted 01: 1 wait state inserted 10: 2 wait states inserted 11: 3 wait states inserted 3 SLFRF 0 R/W Self-Refresh Enable If this bit is set to 1, DRAM/synchronous DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after recovery from software standby mode. 0: Self-refreshing is disabled 1: Self-refreshing is enabled 2 1 0 TPCS2 TPCS1 TPCS0 0 0 0 R/W R/W R/W Self-Refresh Precharge Cycle Control These bits select the number of states in the precharge cycle immediately after selfrefreshing. The number of states in the precharge cycle immediately after self-refreshing are added to the number of states set by bits TPC1 and TPC0 in DRACCR. 000: [TPC set value] states 001: [TPC set value + 1] states 010: [TPC set value + 2] states 011: [TPC set value + 3] states 100: [TPC set value + 4] states 101: [TPC set value + 5] states 110: [TPC set value + 6] states 111: [TPC set value + 7] states Rev. 3.00 Mar 17, 2006 page 151 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. 6.3.12 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. 6.4 6.4.1 Bus Control Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map. Note: Normal mode is not available in this LSI. Rev. 3.00 Mar 17, 2006 page 152 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF H'0000 H'FFFF (1) Advanced mode Note: * Not available in this LSI (2) Normal mode* Figure 6.6 Area Divisions Rev. 3.00 Mar 17, 2006 page 153 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM interface and burst ROM interface, the number of access states may be determined without regard to the setting of ASTCR. When 2-state access space is designated, wait insertion is disabled. When 3-state access space is designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and external waits by means of the WAIT pin. Note: The synchronous DRAM interface is not supported in the H8S/2678 Group. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WTCRA and WTCRB. From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus width, and number of access states and program wait states) for each basic bus interface area. Rev. 3.00 Mar 17, 2006 page 154 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Table 6.2 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WTCRA, WTCRB Wn2 -- 0 Wn1 -- 0 Wn0 -- 0 1 1 0 1 1 0 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 4 5 6 7 8 2 3 0 0 1 2 3 4 5 6 7 1 0 1 -- 0 -- 0 -- 0 1 1 0 1 1 0 0 1 1 (n = 0 to 7) 0 1 Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface space. Chip Select (CS Assertion Period Extension States: Some external I/O devices require a setup CS) CS time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Rev. 3.00 Mar 17, 2006 page 155 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a synchronous DRAM interface* that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the synchronous DRAM interface is designated functions as continuous synchronous DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group. Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM disabled, all of area 0 is external address space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Area 1: In externally expanded mode, all of area 1 is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 1. Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external address space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM space. Rev. 3.00 Mar 17, 2006 page 156 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The OE pin is used as the CKE signal. Area 6: In externally expanded mode, all of area 6 is external space. When area 6 external space is accessed, the CS6 signal can be output. Only the basic bus interface can be used for area 6. Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The onchip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external address space. When area 7 external address space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. 6.4.4 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7 signals output timing. Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit for the port corresponding to the CS0 to CS7 pins. In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS1 to CS7. In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to CS7. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2678R Group, outputs CS2 to CS5 are used as RAS, CAS, WE, and CLK signals. Rev. 3.00 Mar 17, 2006 page 157 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 Address bus Area n external address T2 T3 CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external address space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Rev. 3.00 Mar 17, 2006 page 158 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Upper data bus D15 Lower data bus D0 D8 D7 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus D15 Lower data bus D0 D8 D7 Byte size Byte size Word size Longword size * Even address * Odd address 1st bus cycle 2nd bus cycle Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space) Rev. 3.00 Mar 17, 2006 page 159 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.3 Area 8-bit access space 16-bit access space Data Buses Used and Valid Strobes Access Size Byte Read/ Write Read Write Byte Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Valid Upper Data Bus Lower Data Bus (D15 to D8) (D7 to D0) Valid Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid Notes: Hi-Z: High-impedance state Invalid: Input state; input value is ignored. 6.5.3 Basic Operation Timing 8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Rev. 3.00 Mar 17, 2006 page 160 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev. 3.00 Mar 17, 2006 page 161 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space Rev. 3.00 Mar 17, 2006 page 162 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) Rev. 3.00 Mar 17, 2006 page 163 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev. 3.00 Mar 17, 2006 page 164 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 3.00 Mar 17, 2006 page 165 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) Rev. 3.00 Mar 17, 2006 page 166 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev. 3.00 Mar 17, 2006 page 167 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 3.00 Mar 17, 2006 page 168 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB. Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted in accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the falling edge of in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting seven or more Tw states, or when changing the number of Tw states to be inserted for different external devices. The WAITE bit setting applies to all areas. Figure 6.18 shows an example of wait state insertion timing. The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input disabled. Rev. 3.00 Mar 17, 2006 page 169 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDN = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD Timing RD) RD The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed in basic bus 3-state access space. When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or EDACK. Rev. 3.00 Mar 17, 2006 page 170 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing 6.5.6 Extension of Chip Select (CS Assertion Period CS) CS Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set for individual areas. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Rev. 3.00 Mar 17, 2006 page 171 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Bus cycle Th Address bus CSn AS Read (when RDNn = 0) RD Data bus Read data T1 T2 T3 Tt HWR, LWR Write Data bus Write data Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0). Rev. 3.00 Mar 17, 2006 page 172 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.6.1 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). Table 6.4 RMTS2 0 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space RMTS1 0 1 RMTS0 1 0 1 Area 5 Normal space Normal space DRAM space Area 4 Normal space Normal space DRAM space Area 3 Normal space DRAM space DRAM space Area 2 DRAM space DRAM space DRAM space 1 0 0 1 Continuous synchronous DRAM space* Mode register settings of synchronous DRAM* Reserved (setting prohibited) Continuous DRAM space Continuous DRAM space Continuous DRAM space Continuous DRAM space 1 0 1 Note: * Reserved (setting prohibited) in the H8S/2678 Group. With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait states, etc.) for continuous DRAM space conform to the settings for area 2. 6.6.2 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table 6.5 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be cleared to 0 when the DRAM interface is used. Rev. 3.00 Mar 17, 2006 page 173 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins Shift Size 8 bits A23 to A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A16 A23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 to A16 A23 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 to A16 A23 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 to A16 A23 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 to A16 Reserved (setting prohibited) -- A23 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 to A16 MXC2 MXC1 MXC0 Row address 0 0 0 1 9 bits 1 0 10 bits 1 11 bits 1 Column address 0* x x x x 1* Legend: Note: * x x Reserved (setting prohibited) x: Don't care In the H8S/2678 Group, address pins are A23 to A0. 6.6.3 Data Bus If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, x16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment. Rev. 3.00 Mar 17, 2006 page 174 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5 signals are output. Table 6.6 Pin HWR CS2 DRAM Interface Pins With DRAM Setting WE RAS2/RAS Name Write enable Row address strobe 2/ row address strobe I/O Output Output Function Write enable for DRAM space access Row address strobe when area 2 is designated as DRAM space or row address strobe when areas 2 to 5 are designated as continuous DRAM space Row address strobe when area 3 is designated as DRAM space Row address strobe when area 4 is designated as DRAM space Row address strobe when area 5 is designated as DRAM space Upper column address strobe for 16-bit DRAM space access or column address strobe for 8bit DRAM space access Lower column address strobe signal for 16-bit DRAM space access Output enable signal for DRAM space access Wait request signal Row address/column address multiplexed output Data input/output pins CS3 CS4 CS5 UCAS RAS3 RAS4 RAS5 UCAS Row address strobe 3 Row address strobe 4 Row address strobe 5 Upper column address strobe Output Output Output Output LCAS LCAS Lower column address strobe Output enable Wait Address pins Data pins Output RD, OE WAIT A15 to A0 D15 to D0 OE WAIT A15 to A0 D15 to D0 Output Input Output I/O Rev. 3.00 Mar 17, 2006 page 175 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.5 Basic Timing Figure 6.21 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp Address bus Row address Column address Tr Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0) When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When connecting DRAM provided with an EDO page mode, the OE signal should be connected to the Rev. 3.00 Mar 17, 2006 page 176 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) (OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. 6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.22 shows an example of the timing when a 3-state column address output cycle is selected. Tp Tr Tc1 Tc2 Tc3 Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle (RAST = 0) Rev. 3.00 Mar 17, 2006 page 177 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.23 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state. Tp Tr Tc1 Tc2 Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.23 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0) Rev. 3.00 Mar 17, 2006 page 178 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output. Use the setting that gives the optimum row address signal hold time relative to the falling edge of the RAS signal according to the DRAM connected and the operating frequency of this LSI. Figure 6.24 shows an example of the timing when one Trw state is set. Tp Address bus Row address Column address Tr Trw Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.24 Example of Timing with One Row Address Output Maintenance State (RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 179 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.25 shows the timing when two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Address bus Row address Column address Tp2 Tr Tc1 Tc2 RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High Note: n = 2 to 5 Figure 6.25 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 180 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access. Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings in registers WTCRA and WTCRB. Pin Wait Insertion: When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a program wait (Tw) is first inserted. If the WAIT pin is low at the falling edge of in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figures 6.26 and 6.27 show examples of wait cycle insertion timing in the case of 2-state and 3state column address output cycles. Rev. 3.00 Mar 17, 2006 page 181 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 WAIT Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus UCAS, LCAS WE (HWR) OE (RD) Data bus Row address Column address Read High Write High Notes: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output) Rev. 3.00 Mar 17, 2006 page 182 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 Tc3 WAIT Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus UCAS, LCAS WE (HWR) OE (RD) Data bus Row address Column address Read High Write High Notes: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output) Rev. 3.00 Mar 17, 2006 page 183 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.10 Byte Access Control When DRAM with a x16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and figure 6.29 shows an example of 2-CAS DRAM connection. Tp Address bus Row address Column address Tr Tc1 Tc2 RASn (CSn) UCAS LCAS WE (HWR) OE (RD) Upper data bus High High Write data High-Z Lower data bus Note: n = 2 to 5 Figure 6.28 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 184 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) This LSI (Address shift size set to 10 bits) RASn (CSn) UCAS LCAS HWR (WE) RD (OE) A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 2-CAS type 16-Mbit DRAM 1-Mbyte x 16-bit configuration 10-bit column address RAS UCAS LCAS WE OE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 Figure 6.29 Example of 2-CAS DRAM Connection 6.6.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR. Rev. 3.00 Mar 17, 2006 page 185 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Address bus RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus WE (HWR) Write OE (RD) Data bus Tr Tc1 Tc2 Tc1 Tc2 Row address Column address 1 Column address 2 High High Note: n = 2 to 5 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 186 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Address bus RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus WE (HWR) Write OE (RD) Data bus Note: n = 2 to 5 Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 Row address Column address 1 Column address 2 High High Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details see section 6.6.9, Wait Control. RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. * RAS Down Mode To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed when the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.32 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if: a refresh operation is initiated in the RAS down state Rev. 3.00 Mar 17, 2006 page 187 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) self-refreshing is performed the chip enters software standby mode the external bus is released the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction. Normal space read Tc2 T1 T2 DRAM space read Tc1 Tc2 DRAM space read Tp Tr Tc1 Address bus Row address Column address 1 External address Column address 2 RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.32 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 188 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) * RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of the timing in RAS up mode. DRAM space read Tc2 Tc1 Tc2 Normal space read T1 T2 DRAM space read Tp Tr Tc1 Address bus Row address Column address 1 Column address 2 External address RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.33 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 189 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.6.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the DRAM used. When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is shown in figure 6.34, compare match timing in figure 6.35, and CBR refresh timing in figure 6.36. When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is performed in parallel during the CBR refresh period. RTCNT RTCOR H'00 Refresh request Figure 6.34 RTCNT Operation Rev. 3.00 Mar 17, 2006 page 190 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.35 Compare Match Timing TRp TRr TRc1 TRc2 CSn (RASn) UCAS, LCAS Figure 6.36 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.37 shows the timing when bits RCW1 and RCW0 are set. Rev. 3.00 Mar 17, 2006 page 191 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) TRp TRrw TRr TRc1 TRc2 CSn (RASn) UCAS, LCAS Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and retains its value prior to the start of the refresh period. Rev. 3.00 Mar 17, 2006 page 192 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Normal space access request A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.38 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.39. When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is exited automatically. If a CBR refresh request occurs when making a transition to software standby mode, CBR refreshing is executed, then self-refresh mode is entered. When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register. Rev. 3.00 Mar 17, 2006 page 193 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) TRp TRr Software standby TRc3 CSn (RASn) UCAS, LCAS HWR (WE) Note: n = 2 to 5 High Figure 6.39 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.40 shows an example of the timing when the precharge time immediately after self-refreshing is extended by 2 states. Rev. 3.00 Mar 17, 2006 page 194 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Software standby DRAM space write Trc3 Trp1 Trp2 Tp Tr Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS OE (RD) WR (HWR) Data bus Note: n = 2 to 5 Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCRH. 6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC Rev. 3.00 Mar 17, 2006 page 195 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) or EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1. Tp Tr Tc1 Tc2 Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) High Data bus WE (HWR) Write OE (RD) Data bus High DACK or EDACK Note: n = 2 to 5 Figure 6.41 Example of DACK EDACK Output Timing when DDS = 1 or EDDS = 1 DACK/EDACK (RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 196 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or EDDS = 0. Tp Tr Tc1 Tc2 Tc3 Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read OE (RD) Data bus High WE (HWR) Write OE (RD) Data bus High DACK or EDACK Note: n = 2 to 5 Figure 6.42 Example of DACK EDACK Output Timing when DDS = 0 or EDDS = 0 DACK/EDACK (RAST = 0, CAST = 1) Rev. 3.00 Mar 17, 2006 page 197 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7 Synchronous DRAM Interface In the H8S/2678R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected. Note: The synchronous DRAM interface is not supported in the H8S/2678 Group. 6.7.1 Setting Continuous Synchronous DRAM Space Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings are and continuous area (areas 2 to 5). Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space RMTS1 0 1 RMTS0 1 0 1 1 0 0 1 1 0 1 Area 5 Normal space Normal space DRAM space Area 4 Normal space Normal space DRAM space Area 3 Normal space DRAM space DRAM space Area 2 DRAM space DRAM space DRAM space RMTS2 0 Continuous synchronous DRAM space Mode settings of synchronous DRAM Reserved (setting prohibited) Continuous DRAM space With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is used as synchronous DRAM clock (SDRAM). The bus specifications for continuous synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous synchronous DRAM are invalid. Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and address-precharge-setting command (Prechrge-sel) output on the upper column addresses. Rev. 3.00 Mar 17, 2006 page 198 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.7.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used. Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins Shift A23 to MXC2 MXC1 MXC0 Size A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A16 Row address 0 1 x 0 x 0 1 1 0 1 Column address 0 1 x 0 x 0 1 1 0 1 -- -- -- -- A23 to A16 A23 to A16 A23 to A16 A23 to A16 P P P P P P P P P P P P Reserved (setting prohibited) 8 bits A23 to A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A16 9 bits A23 to A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A16 10 bits A23 to A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A16 11 bits A23 to A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A16 Reserved (setting prohibited) P P P P P P P P P P A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Legend: X: Don't care P: Precharge-sel Rev. 3.00 Mar 17, 2006 page 199 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, x16-bit configuration synchronous DRAM can be connected directly. In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data Size and Data Alignment. 6.7.4 Pins Used for Synchronous DRAM Interface Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation. Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR register to 1 when the CKE signal is output. Rev. 3.00 Mar 17, 2006 page 200 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Table 6.9 Synchronous DRAM Interface Pins With Synchronous DRAM Setting RAS Pin CS2 Name Row address strobe I/O Output Function Row address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space Column address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space Write enable strobe when areas 2 to 5 are designated as continuous synchronous DRAM space Clock only for synchronous DRAM Clock enable signal when areas 2 to 5 are designated as continuous synchronous DRAM space Upper data mask enable for 16-bit continuous synchronous DRAM space access/data mask enable for 8-bit continuous synchronous DRAM space access Lower data mask enable signal for 16-bit continuous synchronous DRAM space access Row address/column address multiplexed output pins Data input/output pins Output enable pin for SDRAM CS3 CAS Column address strobe Output CS4 WE Write enable Output CS5 (OE) SDRAM (CKE) Clock Clock enable Output Output UCAS DQMU Upper data mask enable Output LCAS DQML Lower data mask enable Output A15 to A0 A15 to A0 Address pins Output D15 to D0 DCTL D15 to D0 DCTL Data pins Device control pin I/O Input Rev. 3.00 Mar 17, 2006 page 201 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.5 Synchronous DRAM Clock When the DCTL pin is fixed to 1, synchronous clock (SDRAM) is output from the CS5 pin. When the frequency multiplication factor of the PLL circuit of this LSI is set to x1 or x2, SDRAM is 90 phase shift from . Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between and SDRAM. When the frequency multiplication factor of the PLL circuit is x4, the phase of SDRAM and that of are the same. When the CLK pin of the synchronous DRAM is directly connected to SDRAM of this LSI, it is recommended to set the frequency multiplication factor of the PLL circuit to x1 or x2. Note: SDRAM output timing is shown when the frequency multiplication factor of the PLL circuit is x1 or x2. Tcyc 1/4 Tcyc (90) SDRAMo Figure 6.43 Relationship between and SDRAM (when PLL frequency multiplication factor is x1 or x2) 6.7.6 Basic Operation Timing The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored. Figure 6.44 shows the basic timing for synchronous DRAM. Rev. 3.00 Mar 17, 2006 page 202 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL ACTV NOP WRIT Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev. 3.00 Mar 17, 2006 page 203 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected. The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of synchronous DRAM to be connected. Table 6.10 Setting CAS Latency W22 0 W21 0 W20 0 1 1 0 1 1 0 0 1 1 0 1 Description Connect synchronous DRAM of CAS latency 1 Connect synchronous DRAM of CAS latency 2 Connect synchronous DRAM of CAS latency 3 Connect synchronous DRAM of CAS latency 4 Reserved (must not used) Reserved (must not used) Reserved (must not used) Reserved (must not used) CAS Latency Control Cycle Inserted 0 state 1 state 2 states 3 states -- -- -- -- Rev. 3.00 Mar 17, 2006 page 204 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl1 Tcl2 Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL ACTV NOP WRIT NOP Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev. 3.00 Mar 17, 2006 page 205 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait time according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.46 shows an example of the timing when the one Trw state is set. Rev. 3.00 Mar 17, 2006 page 206 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Trw Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Read Data bus PALL ACTV NOP READ NOP RAS CAS WE CKE DQMU, DQML High Write Data bus PALL ACTV NOP WRIT NOP Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 207 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.47 shows the timing when two Tp states are inserted. Rev. 3.00 Mar 17, 2006 page 208 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Read Data bus PALL NOP ACTV READ NOP RAS CAS WE CKE DQMU, DQML High Write Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.47 Example of Timing with Two-State Precharge Cycle (TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 209 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS latency control cycle is disabled. Tp Tr Tc1 Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Data bus PALL ACTV NOP WRIT Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled (SDWCD = 1) Rev. 3.00 Mar 17, 2006 page 210 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.11 Byte Access Control When synchronous DRAM with a x16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of connection of byte control by DQMU and DQML. Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU High DQML Upper data bus High Lower data bus High-Z PALL ACTV NOP WRIT NOP Figure 6.49 DQMU and DQML Control Timing (Upper Byte Write Access: SDWCD = 0, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 211 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU High High DQML Upper data bus High-Z Lower data bus PALL ACTV READ NOP Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 212 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) 16-Mbit synchronous DRAM 1-Mword x 16 bits x 4-bank configuration 8-bit column address CS2 (RAS) CS3 (CAS) CS4 (WE) UCAS (DQMU) LCAS (DQML) CS5 (SDRAMo) A23 A21 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 RAS CAS WE DQMU DQML CLK A13 (BS1) A12 (BS0) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ15 to DQ0 Row address input: A11 to A0 Column address input: A7 to A0 Bank select address: A13/A12 DCTL OE (CKE) CKE I/O PORT CS Notes: 1. Bank control is not available. 2. The CKE and CS pins must be fixed to 1 when the power supply is input. 3. The CS pin must be fixed to 0 before accessing synchronous DRAM. Figure 6.51 Example of DQMU and DQML Byte Control Rev. 3.00 Mar 17, 2006 page 213 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.12 Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit to 1 in DRAMCR. DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected. Burst Access Operation Timing: Figure 6.52 shows the operation timing for burst access. When there are consecutive access cycles for continuous synchronous DRAM space, the column address output cycles continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR. Rev. 3.00 Mar 17, 2006 page 214 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 Tc1 Tcl Tc2 SDRAM Address bus Column address 1 Row address Column address Column address 2 Precharge-sel Row address RAS CAS WE CKE DQMU, DQML High Read Data bus PALL ACTV READ NOP READ NOP RAS CAS WE CKE DQMU, DQML High Write Data bus PALL ACTV NOP WRIT NOP WRIT NOP Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 215 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode. To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings. The operation corresponding to DRAM RAS up mode is not supported by this LSI. Figure 6.53 shows an example of the timing in RAS down mode. Note, however, the next continuous synchronous DRAM space access is a full access if: * a refresh operation is initiated in the RAS down state * self-refreshing is performed * the chip enters software standby mode * the external bus is released * the BE bit is cleared to 0 * the mode register of the synchronous DRAM is set There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not guaranteed that other row address are accessed in a period in which program execution ensures the value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of the maximum active state time of each bank must be satisfied. When refresh is not used, programs must be developed so that the bank is not in the active state for more than the specified time. Rev. 3.00 Mar 17, 2006 page 216 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Tc2 T1 T2 Tc1 Tcl Tc2 Address bus Column Row address address Row address Column address External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) 6.7.13 Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. Rev. 3.00 Mar 17, 2006 page 217 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Auto Refreshing: To select auto refreshing, set the RFSHE bit to 1 in REFCR. With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting up again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the synchronous DRAM used. When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown in figure 6.54. Since the refresh counter operation is the same as the operation in the DRAM interface, see section 6.6.12, Refresh Control. When the continuous synchronous DRAM space is set, access to external space other than continuous synchronous DRAM space cannot be performed in parallel during the auto refresh period, since the setting of the CBRM bit of REFCR is ignored. TRp TRr TRc1 TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE PALL REF High NOP Figure 6.54 Auto Refresh Timing Rev. 3.00 Mar 17, 2006 page 218 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) When the interval specification from the PLL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.55 shows the timing when one wait state is inserted. Since the setting of bits TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by the RCW1 and RCW0 bits after the precharge cycles. TRp1 TRp2 TRrw TRr TRc1 TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE High PALL NOP REF NOP Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) Rev. 3.00 Mar 17, 2006 page 219 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle. Set the optimum number of waits according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted. TRp TRr TRr1 TRcw TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM. To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the SELF command is issued, as shown in figure 6.57. When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh mode is exited automatically. If an auto refresh request occurs when making a transition to software standby mode, auto refreshing is executed, then self-refresh mode is entered. Rev. 3.00 Mar 17, 2006 page 220 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR. TRp TRr Software standby TRc2 SDRAM Address bus Precharge-sel RAS CAS WE CKE PALL SELF NOP Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the normal precharge time. In this case, too, normal precharging is performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum post-self-refresh precharge time, including this time. Figure 6.58 shows an example of the timing when the precharge time after self-refreshing is extended by 2 states. Rev. 3.00 Mar 17, 2006 page 221 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If synchronous DRAM is connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR. Software Standby: When a transition is made to normal software standby, the PLL command is not output. If synchronous DRAM is connected and DRAM data is to be retained in software standby, self-refreshing must be set. Rev. 3.00 Mar 17, 2006 page 222 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.14 Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes. When the value to be set in the synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of address H'400000 + 2X for 16-bit bus configuration synchronous DRAM. The value of the address signal is fetched at the issuance time of the MRS command as the setting value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.59 shows the setting timing of the mode in the synchronous DRAM. Tp Tr Tc1 Tc2 SDRAM Address bus Mode setting value Precharge-sel Mode setting value RAS CAS WE CKE PALL NOP High MRS NOP Figure 6.59 Synchronous DRAM Mode Setting Timing Rev. 3.00 Mar 17, 2006 page 223 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed. The establishment time for the read data can be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits. (1) Output Timing of DACK or EDACK When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tc1 state. Figure 6.60 shows the DACK or EDACK output timing for the synchronous DRAM interface when DDS = 1 or EDDS = 1. Rev. 3.00 Mar 17, 2006 page 224 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL DACK or RDACK ACTV NOP WRIT NOP Figure 6.60 Example of DACK EDACK Output Timing when DDS = 1 or EDDS = 1 DACK/EDACK Rev. 3.00 Mar 17, 2006 page 225 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.61 shows the DACK or EDACK output timing for the synchronous DRAM interface when DDS = 0 or EDDS = 0. Rev. 3.00 Mar 17, 2006 page 226 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 SDRAM Address bus Column address Row address Column address Precharge-sel Row address RAS CAS WE Read CKE DQMU, DQML High Data bus PALL ACTV READ NOP RAS CAS WE Write CKE DQMU, DQML High Data bus PALL DACK or RDACK ACTV NOP WRIT NOP Figure 6.61 Example of DACK EDACK Output Timing when DDS = 0 or EDDS = 0 DACK/EDACK Rev. 3.00 Mar 17, 2006 page 227 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended. The extension of the read data is not in accordance with the bits DDS and EDDS. Figure 6.62 shows the timing chart when the read data is extended by two cycles. Tp Tr Tc1 Tcl Tc2 Tsp1 Tsp2 SDRAM Address bus Row Column address address Row address Column address Precharge-sel RAS CAS WE CKE DQMU, DQML Data bus DACK or EDACK PALL ACTV READ NOP Figure 6.62 Example of Timing when the Read Data Is Extended by Two States (DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 228 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.8 Burst ROM Interface In this LSI, external space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space interface enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for burst access. Settings can be made independently for area 0 and area 1. In burst ROM interface space, burst access covers only CPU read accesses. 6.8.1 Basic Timing The number of access states in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and CSACRH. When area 0 or area 1 is designated as burst ROM interface space, the settings in RDNCR and CSACRL are ignored. From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and BSTS10 in BROMCR. The basic access timing for burst ROM space is shown in figures 6.63 and 6.64. Rev. 3.00 Mar 17, 2006 page 229 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Full access T1 T2 T3 T1 Burst access T2 T1 T2 Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 3.00 Mar 17, 2006 page 230 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.8.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. 6.8.3 Write Access When a write access to burst ROM interface space is executed, burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings. Write accesses are not performed in burst mode even though burst ROM space is designated. Rev. 3.00 Mar 17, 2006 page 231 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.9 6.9.1 Idle Cycle Operation When this LSI accesses external space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle (in the H8S/2678R Group, it cannot insert an idle cycle in the condition (3)). Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and so on. Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle. Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 Address bus CS (area A) CS (area B) RD Data bus T2 T3 Bus cycle B T1 T2 Address bus CS (area A) CS (area B) RD Data bus Data collision Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Long output floating time (a) No idle cycle insertion (ICIS1 = 0) Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) Rev. 3.00 Mar 17, 2006 page 232 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD HWR Data bus Address bus CS (area A) CS (area B) RD HWR Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS0 = 0) Idle cycle (b) Idle cycle insertion (ICIS0 = 1, initial value) Figure 6.66 Example of Idle Cycle Operation (Write after Read) Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle cycle is inserted at the start of the read cycle. Figure 6.67 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an external device. In (b), an idle cycle is inserted, and a data collision is prevented. Note: In the H8S/2678 Group, an idle cycle cannot be inserted in the condition (3). Rev. 3.00 Mar 17, 2006 page 233 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD HWR, LWR Data bus Address bus CS (area A) CS (area B) RD HWR Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS2 = 0) Idle cycle (b) Idle cycle insertion (ICIS2 = 1, initial value) Figure 6.67 Example of Idle Cycle Operation (Read after Write) Relationship between Chip Select (CS Signal and Read (RD Signal: Depending on the CS) RD) CS RD system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Rev. 3.00 Mar 17, 2006 page 234 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS (area A) CS (area B) RD Address bus CS (area A) CS (area B) RD Overlap period between CS (area B) and RD may occur (a) No idle cycle insertion (ICIS1 = 0) Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 6.68 Relationship between Chip Select (CS and Read (RD CS) RD) CS RD Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space access following a normal space access, the settings of bits ICIS2 (not available in the H8S/2678 Group), ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.69. External read DRAM space read T1 T2 T3 Tp Tr Tc1 Tc2 Address bus RD Data bus Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0) In burst access in RAS down mode, the settings of bits ICIS2 (not available in the H8S/2678 Group), ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71. Rev. 3.00 Mar 17, 2006 page 235 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) DRAM space read External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 Ti Tc1 Tc2 Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read External read DRAM space write Tp Tr Tc1 Tc2 T1 T2 T3 Ti Tc1 Tc2 Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 236 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access: In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in figure 6.72. Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported. External space read Synchronous DRAM space read T1 Address bus T2 T3 Tp Tr Tc1 Tcl Tc2 Row Column address address Row address Column address Precharge-sel RAS CAS WE CKE DQMU, DQML RD Data bus NOP PALL ACTV READ NOP Figure 6.72 Example of Synchronous DRAM Full Access after External Read (CAS Latency 2) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.73 Rev. 3.00 Mar 17, 2006 page 237 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) and 6.74. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit. The timing in this case is illustrated in figure 6.75. Continuous synchronous DRAM space read Continuous synchronous DRAM space read External space read Tp Address bus Tr Tc1 Tcl Tc2 T1 T2 T3 Ti Tc1 TCl Tc2 Row Column address address Row address Column address 1 External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus High PALL ACTV READ NOP READ NOP Idle cycle Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 238 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 Address bus Row Column address address Row address Column address 1 External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus High PALL ACTV READ NOP READ NOP Idle cycle Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 239 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space write Tp Tr Tc1 Tcl Tc2 T1 T2 T3 Ti Tc1 TCl Tc2 Address bus Row Column address address Row address Column address 1 External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus High PALL ACTV READ NOP WRIT NOP Idle cycle Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2) Idle Cycle in Case of Normal Space Access after DRAM Space Access: * Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show examples of idle cycle operation when the DRMI bit is set to 1. Rev. 3.00 Mar 17, 2006 page 240 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if bits ICIS1 and ICIS0 are set to 1. DRAM space read External read DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Ti Tc1 Tc2 Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) Rev. 3.00 Mar 17, 2006 page 241 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) DRAM space read External write DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Tc1 Tc2 Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) * Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR (there is no ICRS2 bit in the H8S/2678 Group, therefore this setting cannot be made) and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1. Rev. 3.00 Mar 17, 2006 page 242 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) DRAM space read External space read DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Tc1 Tc2 Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space Access: Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported. * Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.79 shows an example of idle cycle operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and ICIS0 are set to 1. Rev. 3.00 Mar 17, 2006 page 243 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read External space read Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Tc2 Ti T1 T2 T3 Ti Tc1 TCl Tc2 Address bus Precharge-sel RAS Row Column address address Row address Column address 1 External address External address Column address 2 CAS WE CKE High DQMU, DQML RD Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2) * Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is not in accordance with the DRMI bit in DRACCR. Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1. Rev. 3.00 Mar 17, 2006 page 244 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write External space read Continuous synchronous DRAM space read Tp Tr Tc1 Tc2 Ti T1 T2 T3 Tc1 TCl Tc2 Address bus Row Column address address Row address Column address External address Column address 2 Precharge-sel RAS External address CAS WE CKE High DQMU, DQML RD HWR, LWR Data bus PALL ACTV NOP WRIT NOP READ NOP Idle cycle Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space/continuous synchronous DRAM space. Rev. 3.00 Mar 17, 2006 page 245 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space Previous Access Normal space read Next Access Normal space read (different area) ICIS2* -- -- -- -- -- -- DRAM/continuous synchronous DRAM* space write DRAM/continuous Normal space read synchronous DRAM* space read -- -- -- -- ICIS1 0 1 0 1 -- -- -- -- 0 1 ICIS0 -- -- -- -- 0 1 0 1 -- -- DRMI -- -- -- -- -- -- -- -- -- 0 1 -- -- 0 1 -- -- -- 0 1 -- -- -- -- 0 1 -- 0 1 DRAM/continuous synchronous DRAM* space write -- -- -- -- 0 1 -- 0 1 0 1 -- -- -- -- -- -- IDLC -- 0 1 DRAM/continuous synchronous DRAM* space read Normal space write -- 0 1 -- 0 1 -- 0 1 -- -- 0 1 DRAM/continuous synchronous DRAM* space read -- -- 0 1 Normal space write -- -- 0 1 -- -- 0 1 Normal space write Normal space read -- 0 1 DRAM/continuous synchronous DRAM* space read 0 1 -- -- -- -- -- -- -- 0 1 Idle cycle Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Rev. 3.00 Mar 17, 2006 page 246 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Previous Access Next Access ICIS2* 0 1 0 1 ICIS1 -- -- -- -- ICIS0 -- -- -- -- DRMI -- -- -- -- IDLC -- 0 1 -- 0 1 Idle cycle Disabled 1 state inserted 2 states inserted Disabled 1 state inserted 2 states inserted Normal space read DRAM/continuous synchronous DRAM* space write DRAM/continuous synchronous DRAM * space read Note: * In the H8S/2678 Group, the synchronous DRAM interface is not supported. Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in DRAM/continuous synchronous DRAM space burst access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to DRAM/continuous synchronous DRAM space. DRAM space read DRAM space write Tp Tr Tc1 Tc2 Ti Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus Note: n = 2 to 5 Idle cycle Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode Rev. 3.00 Mar 17, 2006 page 247 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Continuous synchronous DRAM space write Tp Tr Tc1 Tcl Tc2 Ti Tc1 Tc2 Address bus Precharge-sel RAS Column Row address address Column address External address CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev. 3.00 Mar 17, 2006 page 248 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.9.2 Pin States in Idle Cycle Table 6.12 shows the pin states in an idle cycle. Table 6.12 Pin States in Idle Cycle Pins A23 to A0 D15 to D0 CSn (n = 7 to 0) UCAS, LCAS AS RD (OE) HWR, LWR DACKn (n = 1, 0) EDACKn (n = 3 to 0) Pin State Contents of following bus cycle High impedance 12 High* * High* High High High High High High 2 Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle. 6.10 Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCR. Figure 6.83 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. Rev. 3.00 Mar 17, 2006 page 249 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address CSn External space write HWR, LWR D15 to D0 Figure 6.83 Example of Timing when Write Data Buffer Function is Used 6.11 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally. * When an internal bus master wants to perform an external access * When a refresh request is generated * When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode Rev. 3.00 Mar 17, 2006 page 250 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.11.1 Operation In externally expanded mode, the bus can be released to an external device by setting the BRLE bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. In the external bus released state, internal bus masters except the EXDMAC can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. If a refresh request is generated in the external bus released state, or if a SLEEP instruction is executed to place the chip in software standby mode or all-module-clocksstopped mode, refresh control and software standby or all-module-clocks-stopped control is deferred until the bus request from the external bus master is canceled. If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the following requests are issued, to request cancellation of the bus request externally. * When an internal bus master wants to perform an external access * When a refresh request is generated * When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > External access by internal bus master (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) Rev. 3.00 Mar 17, 2006 page 251 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.11.2 Pin States in External Bus Released State Table 6.13 shows pin states in the external bus released state. Table 6.13 Pin States in Bus Released State Pins A23 to A0 D15 to D0 CSn (n = 7 to 0) UCAS, LCAS AS RD (OE) HWR, LWR DACKn (n = 1, 0) EDACKn (n = 3 to 0) Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High High Rev. 3.00 Mar 17, 2006 page 252 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.11.3 Transition Timing Figure 6.84 shows the timing for transition to the bus released state. External space access cycle External bus released state T1 High-Z T2 CPU cycle Address bus High-Z Data bus High-Z AS High-Z RD High-Z HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [7] [8] [1] Low level of BREQ signal is sampled at rise of o. [2] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [3] BACK signal is driven low, releasing bus to external bus master. [4] BREQ signal state is also sampled in external bus released state. [5] High level of BREQ signal is sampled. [6] BACK signal is driven high, ending external bus release cycle. [7] When there is external access or refresh request of internal bus master during external bus release while BREQOE bit is set to 1, BREQO signal goes low. [8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. Figure 6.84 Bus Released State Transition Timing Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM interface. Rev. 3.00 Mar 17, 2006 page 253 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) External space read T1 T2 External bus released state CPU cycle SDRAM High-Z Address bus High-Z Data bus High-Z Precharge-sel Row address High-Z RAS High-Z CAS High-Z WE High-Z CKE High-Z DQMU, DQML BREQ BACK BREQO NOP [1] [2] PALL [3] NOP [4] [5] [8] [6] [7] NOP [9] [1] Low level of BREQ signal is sampled at rise of f. [2] PLL command is issued. [3] Bus control signal returns to be high at end of external space access cycle. At least one state from sampling of BREQ signal. [4] BACK signal is driven low, releasing bus to external bus master.. [5] BREQ signal state is also sampled in external bus released state. [6] High level of BREQ signal is sampled. [7] BACK signal is driven high, ending external bus release cycle. [8] When there is external access or refresh request of internal bus master during external bus release while the BREQOE bit is set to 1, BREQO signal goes low. [9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up. Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface Rev. 3.00 Mar 17, 2006 page 254 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.12 Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus masters--the CPU, DTC, DMAC, and EXDMAC--that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.12.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus mastership is as follows: (High) EXDMAC > DMAC > DTC > CPU (Low) An internal bus access by internal bus masters except the EXDMAC and external bus release, a refresh when the CBRM bit is 0, and an external bus access by the EXDMAC can be executed in parallel. If an external bus release request, a refresh request, and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (High) Refresh > EXDMAC > External bus release (Low) (High) External bus release > External access by internal bus master except EXDMAC (Low) As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to DRAM space by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. 6.12.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus. Rev. 3.00 Mar 17, 2006 page 255 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. * With bit manipulation instructions such as BSET and BCLR, the sequence of operations is: data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is not transferred during this read-modify-write cycle, which is executed as a series of bus cycles. * If the CPU is in sleep mode, the bus is transferred immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. However, in the event of an EXDMAC or external bus release request, which have a higher priority than the DMAC, the bus may be transferred to the bus master even if block or burst transfer is in progress. EXDMAC: The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated. As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in parallel. In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode, after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify Rev. 3.00 Mar 17, 2006 page 256 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) temporary release of the bus in the event of an external access request from an internal bus master. For details see section 8, EXDMA Controller. External Bus Release: When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. 6.13 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.14 6.14.1 Usage Notes External Bus Release Function and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus controller and I/O ports. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is executed in the external bus released state, the transition to all-module-clocks-stopped mode is deferred and performed until after the bus is recovered. 6.14.2 External Bus Release Function and Software Standby In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby state. Rev. 3.00 Mar 17, 2006 page 257 of 926 REJ09B0283-0300 Section 6 Bus Controller (BSC) 6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR refresh/auto refresh request is issued. Note: In the H8S/2678 Group, the auto refresh control is not supported. 6.14.4 BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. 6.14.5 Notes on Usage of the Synchronous DRAM Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the synchronous DRAM interface. Do not change the DCTL pin during operation. Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to SDRAM. WAIT Pin: In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is disabled regardless of the setting of the WAITE bit in BCR. Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected. Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported. When setting the mode register of the synchronous DRAM, set to the burst read/single write and set the burst length to 1. CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the DRAMCR. Rev. 3.00 Mar 17, 2006 page 258 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1 Features * Selectable as short address mode or full address mode Short address mode Maximum of 4 channels can be used Dual address mode or single address mode can be selected In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits In single address mode, transfer source or transfer destination address only is specified as 24 bits In single address mode, transfer can be performed in one bus cycle Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer source and transfer destination addresses as specified as 24 bits Choice of normal mode or block transfer mode * 16-Mbyte address space can be specified directly * Byte or word can be set as the transfer unit * Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception complete interrupt A/D converter conversion end interrupt External request Auto-request * Module stop mode can be set DMAS260A_010020020400 Rev. 3.00 Mar 17, 2006 page 259 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DMTEND0A DMTEND0B DMTEND1A DMTEND1B Address buffer Processor Channel 1B Channel 1A Channel 0B Channel 0A MAR_0AH MAR_0AL ETCR_0A Module data bus Control logic Channel 0 IOAR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer Channel 1 Internal data bus Legend: DMAWER DMATCR DMABCR DMACR MAR IOAR ETCR : DMA write enable register : DMA terminal control register : DMA band control register (for all channels) : DMA control register : Memory address register : I/O address register : Execute transfer count register Figure 7.1 Block Diagram of DMAC Rev. 3.00 Mar 17, 2006 page 260 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 shows the DMAC pin configuration. Table 7.1 Channel 0 Pin Configuration Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 Symbol DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 I/O Input Output Output Input Output Output Function Channel 0 external request Channel 0 single address transfer acknowledge Channel 0 transfer end Channel 1 external request Channel 1 single address transfer acknowledge Channel 1 transfer end 1 DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1 7.3 Register Descriptions * Memory address register_0AH (MAR_0AH) * Memory address register_0AL (MAR_0AL) * I/O address register_0A (IOAR_0A) * Transfer count register_0A (ECTR_0A) * Memory address register_0BH (MAR_0BH) * Memory address register_0BL (MAR_0BL) * I/O address register_0B (IOAR_0B) * Transfer count register_0B (ECTR_0B) * Memory address register_1AH (MAR_1AH) * Memory address register_1AL (MAR_1AL) * I/O address register_1A (IOAR_1A) * Transfer count register_1A (ETCR_1B) * Memory address register_1BH (MAR_1BH) * Memory address register_1BL (MAR_1BL) * I/O address register_1B (IOAR_1B) * Transfer count register_1B (ETCR_1B) * DMA control register_0A (DMACR_0A) * DMA control register_0B (DMACR_0B) Rev. 3.00 Mar 17, 2006 page 261 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) * DMA control register_1A (DMACR_1A) * DMA control register_1B (DMACR_1B) * DMA band control register H (DMABCRH) * DMA band control register L (DMABCRL) * DMA write enable register (DMAWER) * DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and full address mode of channel 0 are shown in table 7.2. Table 7.2 FAE0 0 Short Address Mode and Full Address Mode (Channel 0) Description Short address mode specified (channels 0A and 0B operate independently) Channel 0A MAR_0AH MAR_0AL IOAR_0A ETCR_0A DMACR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B DMACR_0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source. 1 Full address mode specified (channels 0A and 0B operate in combination as channel 0) MAR_0AH MAR_0BH Channel 0 MAR_0AL MAR_0BL IOAR_0A IOAR_0B ETCR_0A ETCR_0B Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. DMACR_0A DMACR_0B Rev. 3.00 Mar 17, 2006 page 262 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0 (channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B). MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. Full Address Mode: In full address mode, MARA functions as the source address register, and MARB as the destination address register. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination address is constantly updated. 7.3.2 I/O Address Registers (IOARA and IOARB) IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address (transfer source address) or destination address (transfer destination address). The upper 8 bits of the transfer address are automatically set to H'FF. The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0 (channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B). Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is not incremented or decremented each time a data transfer is executed, so the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. IOAR can be used in short address mode but not in full address mode. Rev. 3.00 Mar 17, 2006 page 263 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode. Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends. In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCRL is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. Full Address Mode: The function of ETCR in normal mode differs from that in block transfer mode. In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used in normal mode. In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH functions as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev. 3.00 Mar 17, 2006 page 264 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together. The bit functions in the DMACR registers differ according to the transfer mode. Short Address Mode: * DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B Bit 7 Bit Name DTSZ Initial Value 0 R/W R/W Description Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 6 DTID 0 R/W Data Transfer Increment/Decrement Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. 0: MAR is incremented after a data transfer (Initial value) * * * * When DTSZ = 0, MAR is incremented by 1 When DTSZ = 1, MAR is incremented by 2 When DTSZ = 0, MAR is decremented by 1 When DTSZ = 1, MAR is decremented by 2 1: MAR is decremented after a data transfer Rev. 3.00 Mar 17, 2006 page 265 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 5 Bit Name RPE Initial Value 0 R/W R/W Description Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. * When DTIE = 0 (no transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in repeat mode * When DTIE = 1 (with transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in idle mode 4 DTDIR 0 R/W Data Transfer Direction Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. * When SAE = 0 0: Transfer with MAR as source address and DACK pin as write strobe 1: Transfer with DACK pin as read strobe and MAR as destination address * When SAE = 1 0: Transfer with MAR as source address and IOAR as destination address 1: Transfer with IOAR as source address and MAR as destination address 3 2 1 0 DTF3 DTF2 DTF1 DTF0 0 0 0 0 R/W R/W R/W R/W Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B. Rev. 3.00 Mar 17, 2006 page 266 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description * Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited Rev. 3.00 Mar 17, 2006 page 267 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description * Channel B 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin rising edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Rev. 3.00 Mar 17, 2006 page 268 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Full Address Mode: * DMACR_0A and DMACR_1A Bit 15 Bit Name DTSZ Initial Value 0 R/W R/W Description Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer 14 13 SAID SAIDE 0 0 R/W R/W Source Address Increment/Decrement Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARA is fixed 01: MARA is incremented after a data transfer * * When DTSZ = 0, MARA is incremented by 1 When DTSZ = 1, MARA is incremented by 2 10: MARA is fixed 11: MARA is decremented after a data transfer * * 12 11 BLKDIR BLKE 0 0 R/W R/W When DTSZ = 0, MARA is decremented by 1 When DTSZ = 1, MARA is decremented by 2 Block Direction Block Enable These bits specify whether normal mode or block transfer mode is to be used for data transfer. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. x0: Transfer in normal mode 01: Transfer in block transfer mode (destination side is block area) 11: Transfer in block transfer mode (source side is block area) Rev. 3.00 Mar 17, 2006 page 269 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 10 to 8 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits can be read from or written to. However, the write value should always be 0. Legend: x: Don't care * DMACR_0B and DMACR_1B Bit 7 Bit Name Initial Value 0 R/W R/W Description Reserved This bit can be read from or written to. However, the write value should always be 0. 6 5 DAID DAIDE 0 0 R/W R/W Destination Address Increment/Decrement Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. 00: MARB is fixed 01: MARB is incremented after a data transfer * * When DTSZ = 0, MARB is incremented by 1 When DTSZ = 1, MARB is incremented by 2 10: MARB is fixed 11: MARB is decremented after a data transfer * * 4 -- 0 R/W When DTSZ = 0, MARB is decremented by 1 When DTSZ = 1, MARB is decremented by 2 Reserved This bit can be read from or written to. However, the write value should always be 0. 3 2 1 0 DTF3 DTF2 DTF1 DTF0 0 0 0 0 R/W R/W R/W R/W Data Transfer Factor 3 to 0 These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. Rev. 3.00 Mar 17, 2006 page 270 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description * Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1xxx: Setting prohibited * Block Transfer Mode 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt 0111: Activated by SCI channel 1 reception complete interrupt 1000: Activated by TPU channel 0 compare match/input capture A interrupt 1001: Activated by TPU channel 1 compare match/input capture A interrupt 1010: Activated by TPU channel 2 compare match/input capture A interrupt 1011: Activated by TPU channel 3 compare match/input capture A interrupt 1100: Activated by TPU channel 4 compare match/input capture A interrupt Rev. 3.00 Mar 17, 2006 page 271 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 1101: Activated by TPU channel 5 compare match/input capture A interrupt 1110: Setting prohibited 1111: Setting prohibited The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend: x: Don't care 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR registers differ according to the transfer mode. Short Address Mode: * DMABCRH Bit 15 Bit Name FAE1 Initial Value 0 R/W R/W Description Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. 0: Short address mode 1: Full address mode Rev. 3.00 Mar 17, 2006 page 272 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 13 Bit Name SAE1 Initial Value 0 R/W R/W Description Single Address Enable 1 Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode 11 10 9 8 DTA1B DTA1A DTA0B DTA0A 0 0 0 0 R/W R/W R/W R/W Data Transfer Acknowledge 1B Data Transfer Acknowledge 1A Data Transfer Acknowledge 0B Data Transfer Acknowledge 0A These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR. It the DTA bit is set to 1 when DTE = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. If the DTA bit is cleared to 0 when DTE = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Rev. 3.00 Mar 17, 2006 page 273 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) * DMABCRL Bit 7 6 5 4 Bit Name DTE1B DTE1A DTE0B DTE0A Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Data Transfer Enable 1B Data Transfer Enable 1A Data Transfer Enable 0B Data Transfer Enable 0A If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the DTF3 to DTF0 bits in DMACR. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] * When initialization is performed * When the specified number of transfers have been completed in a transfer mode other than repeat mode * When 0 is written to the DTE bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE bit after reading DTE = 0 3 2 1 0 DTIE1B DTIE1A DTIE0B DTIE0A 0 0 0 0 R/W R/W R/W R/W Data Transfer End Interrupt Enable 1B Data Transfer End Interrupt Enable 1A Data Transfer End Interrupt Enable 0B Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Rev. 3.00 Mar 17, 2006 page 274 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Full Address Mode: * DMABCRH Bit 15 Bit Name FAE1 Initial Value 0 R/W R/W Description Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as channel 0. 0: Short address mode 1: Full address mode 13, 12 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 275 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 11 Bit Name DTA1 Initial Value 0 R/W R/W Description Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE1 = 1 and DTA1 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA1 bit is cleared to 0 when DTE1 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE1 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA1 bit setting. The state of the DTME1 bit does not affect the above operations. 10 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 276 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 9 Bit Name DTA0 Initial Value 0 R/W R/W Description Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC. It the DTA0 bit is cleared to 0 when DTE0 = 1, the internal interrupt source is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE0 = 0, the internal interrupt source issues an interrupt request to the CPU or DTC regardless of the DTA0 bit setting. The state of the DTME0 bit does not affect the above operations. 8 -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. Rev. 3.00 Mar 17, 2006 page 277 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) * DMABCRL Bit 7 Bit Name DTME1 Initial Value 0 R/W R/W Description Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME1 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME1 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions] * * * When initialization is performed When NMI is input in burst mode When 0 is written to the DTME1 bit [Setting condition] When 1 is written to DTME1 after reading DTME1 = 0 Rev. 3.00 Mar 17, 2006 page 278 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 6 Bit Name DTE1 Initial Value 0 R/W R/W Description Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE1 bit is set to 1 when DTE1 = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE1 = 1 and DTME1 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] * * * When initialization is performed When the specified number of transfers have been completed When 0 is written to the DTE1 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE1 bit after reading DTE1 = 0 Rev. 3.00 Mar 17, 2006 page 279 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 5 Bit Name DTME0 Initial Value 0 R/W R/W Description Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME0 bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME0 bit is not cleared by an NMI interrupt, and transfer is not interrupted. [Clearing conditions] * * * When initialization is performed When NMI is input in burst mode When 0 is written to the DTME0 bit [Setting condition] When 1 is written to DTME0 after reading DTME0 = 0 Rev. 3.00 Mar 17, 2006 page 280 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 4 Bit Name DTE0 Initial Value 0 R/W R/W Description Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTE0 bit is cleared to 0 when DTIE0 = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. When DTE0 = 1 and DTME0 = 1, data transfer is enabled and the DMAC waits for a request by the activation source. When a request is issued by the activation source, DMA transfer is executed. [Clearing conditions] * * * When initialization is performed When the specified number of transfers have been completed When 0 is written to the DTE0 bit to forcibly suspend the transfer, or for a similar reason [Setting condition] When 1 is written to the DTE0 bit after reading DTE0 = 0 3 DTIE1B 0 R/W Data Transfer Interrupt Enable 1B Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME1 bit is cleared to 0 when DTIE1B = 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE1B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME1 bit to 1. Rev. 3.00 Mar 17, 2006 page 281 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bit 2 Bit Name DTIE1A Initial Value 0 R/W R/W Description Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 0 when DTIE1A= 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE1A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE1 bit to 1. 1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B Enables or disables an interrupt to the CPU or DTC when transfer on channel 1 is interrupted. If the DTME0 bit is cleared to 0 when DTIE0B= 1, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIE0B bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME0 bit to 1. 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE0 bit is cleared to 0 when DTIE0A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE0A bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE0 bit to 1. Rev. 3.00 Mar 17, 2006 page 282 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Bit 7 to 4 3 Bit Name Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. WE1B 0 R/W Write Enable 1B Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR. 0: Writes are disabled 1: Writes are enabled 2 WE1A 0 R/W Write Enable 1A Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR. 0: Writes are disabled 1: Writes are enabled 1 WE0B 0 R/W Write Enable 0B Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. 0: Writes are disabled 1: Writes are enabled 0 WE0A 0 R/W Write Enable 0A Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. 0: Writes are disabled 1: Writes are enabled Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt request, and reactivating channel 0A. The address register and count register areas are set again during the first DTC transfer, then the control register area is set again during the second DTC Rev. 3.00 Mar 17, 2006 page 283 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. First transfer area MAR_0A IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A DTC IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B DMAWER DMACR_0A DMACR_1A Second transfer area using chain transfer DMATCR DMACR_0B DMACR_1B DMABCR Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When modifying these registers, the channel to be modified should be halted. Rev. 3.00 Mar 17, 2006 page 284 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The TEND pin is available only for channel B in short address mode. Except for the block transfer mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal asserts in the transfer cycle in which the block counter contents reaches 0. Bit 7, 6 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 5 TEE1 0 R/W Transfer End Enable 1 Enables or disables transfer end pin 1 (TEND1) output. 0: TEND1 pin output disabled 1: TEND1 pin output enabled 4 TEE0 0 R/W Transfer End Enable 0 Enables or disables transfer end pin 0 (TEND0) output. 0: TEND0 pin output disabled 1: TEND0 pin output enabled 3 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 285 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.4 Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Channels 0A and 1A O O O O O O O O O O O X X X Channels 0B and 1B O O O O O O O O O O O O O X Full Address Mode Normal Mode X X X X X X X X X X X O O O Block Transfer Mode O O O O O O O O O O O O O X Activation Source Internal interrupts ADI TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External requests DREQ pin falling edge input DREQ pin low-level input Auto-request Legend: O: Can be specified X: Cannot be specified Rev. 3.00 Mar 17, 2006 page 286 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.4.1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant. If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With ADI, TXI and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0 after completion of a transfer, an interrupt request from the selected activation source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant interrupt request is sent to the CPU or DTC. When an interrupt request signal for DMAC activation is also used for an interrupt request to the CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC. 7.4.2 Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below. When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is detected on the DREQ pin. The next data transfer may not be performed if the next edge is input before data transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Rev. 3.00 Mar 17, 2006 page 287 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.4.3 Activation by Auto-Request Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC keeps possession of the bus until the end of the transfer so that transfer is performed continuously. 7.5 7.5.1 Operation Transfer Modes Table 7.4 lists the DMAC transfer modes. Table 7.4 DMAC Transfer Modes Transfer Source * TPU channel 0 to 5 compare match/input capture A interrupt * SCI transmission complete interrupt * SCI reception complete interrupt * A/D converter conversion end interrupt * External request Remarks * Up to 4 channels can operate independently * External request applies to channel B only * Single address mode applies to channel B only Transfer Mode Short address mode Dual address mode (1) Sequential mode * Memory address incremented or decremented by 1 or 2 * Number of transfers: 1 to 65,536 (2) Idle mode * Memory address fixed * Number of transfers: 1 to 65,536 (3) Repeat mode * Memory address incremented or decremented by 1 or 2 * Continues transfer after sending number of transfers (1 to 256) and restoring the initial value Single address mode * 1-byte or 1-word transfer for a single transfer request * 1-bus cycle transfer by means of DACK pin instead of using address for specifying I/O * Sequential mode, idle mode, or repeat mode can be specified * External request Rev. 3.00 Mar 17, 2006 page 288 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Transfer Mode Full address mode Normal mode (1) Auto-request * Transfer request is internally held * Number of transfers (1 to 65,536) is continuously sent * Burst/cycle steal transfer can be selected (2) External request * 1-byte or 1-word transfer for a single transfer request * Number of transfers: 1 to 65,536 Block transfer mode * Transfer of 1-block, size selected for a single transfer request * Number of transfers: 1 to 65,536 * Source or destination can be selected as block area * Block size: 1 to 256 bytes or word * TPU channel 0 to 5 compare match/input capture A interrupt * SCI transmission complete interrupt * SCI reception complete interrupt * A/D converter conversion end interrupt * External request External request Transfer Source Auto-request Remarks * Max. 2-channel operation, combining channels A and B Rev. 3.00 Mar 17, 2006 page 289 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.5 Register Functions in Sequential Mode Function Register 23 MAR 23 H'FF 15 ETCR DTDIR = 0 0 DTDIR = 1 Initial Setting Operation Incremented/ decremented every transfer Fixed Source address register Destination Start address of address transfer destination register or transfer source Start address of transfer source or transfer destination Number of transfers 15 IOAR 0 0 Destination Source address address register register Transfer counter Decremented every transfer; transfer ends when count reaches H'0000 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.3 illustrates operation in sequential mode. Rev. 3.00 Mar 17, 2006 page 290 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (-1)DTID * (2DTSZ * (N - 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.4 shows an example of the setting procedure for sequential mode. Rev. 3.00 Mar 17, 2006 page 291 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Sequential mode setting [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Clear the RPE bit to 0 to select sequential mode. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set the DTE bit to 1 to enable transfer. Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 7.4 Example of Sequential Mode Setting Procedure 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other Rev. 3.00 Mar 17, 2006 page 292 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register 23 MAR 23 H'FF 15 ETCR DTDIR = 0 0 DTDIR = 1 Initial Setting Operation Fixed Source address register Destination Start address of address transfer destination register or transfer source Start address of transfer source or transfer destination Number of transfers 15 IOAR 0 0 Destination Source address address register register Transfer counter Fixed Decremented every transfer; transfer ends when count reaches H'0000 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. Figure 7.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Rev. 3.00 Mar 17, 2006 page 293 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Figure 7.6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Set the RPE bit to 1. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Set the DTIE bit to 1. * Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7.6 Example of Idle Mode Setting Procedure Rev. 3.00 Mar 17, 2006 page 294 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register 23 MAR 0 DTDIR = 0 Source address register DTDIR = 1 Initial Setting Operation Incremented/ decremented every transfer. Initial setting is restored when value reaches H'0000 Fixed Destination Start address of address transfer destination register or transfer source 23 H'FF 15 IOAR 0 Destination Source address address register register Holds number of transfers Start address of transfer source or transfer destination 7 ETCRH 0 Number of transfers Fixed 7 ETCRL 0 Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when count reaches H'00 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. Rev. 3.00 Mar 17, 2006 page 295 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR - (-1) DTID *2 DTSZ * ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (-1)DTID * (2DTSZ * (N - 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.7 Operation in Repeat mode Rev. 3.00 Mar 17, 2006 page 296 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Set the RPE bit to 1. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Clear the DTIE bit to 0. * Set the DTE bit to 1 to enable transfer. Repeat mode setting Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 7.8 Example of Repeat Mode Setting Procedure Rev. 3.00 Mar 17, 2006 page 297 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function Register 23 MAR 0 DTDIR = 0 DTDIR = 1 Source address register Initial Setting Operation See sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. Strobe for external device Destination Start address of address transfer destination register or transfer source DACK pin Write strobe 0 Read strobe (Set automatically by SAE bit; IOAR is invalid) 15 ETCR Transfer counter Number of transfers See sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output. Figure 7.9 illustrates operation in single address mode (when sequential mode is specified). Rev. 3.00 Mar 17, 2006 page 298 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Address T Transfer DACK 1-byte or -word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (-1)DTID * (2DTSZ * (N - 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Rev. 3.00 Mar 17, 2006 page 299 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Single address mode setting Set DMABCRH [1] [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Set the SAE bit to 1 to select single address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. Set transfer source and transfer destination addresses [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Clear the RPE bit to 0 to select sequential mode. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set the DTE bit to 1 to enable transfer. Set DMABCRL [6] Single address mode Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is Specified) Rev. 3.00 Mar 17, 2006 page 300 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register 23 MARA 23 MARB 15 ETCRA 0 Register Functions in Normal Mode Function 0 Initial Setting Start address of transfer source Start address of transfer destination Number of transfers Operation Incremented/ decremented every transfer, or fixed Incremented/ decremented every transfer, or fixed Decremented every transfer; transfer ends when count reaches H'0000 Source address register Destination address register Transfer counter 0 MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Figure 7.11 illustrates operation in normal mode. Rev. 3.00 Mar 17, 2006 page 301 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Address TA Transfer Address TB Address BA Legend: Address Address Address Address Where: Address BB TA TB BA BB LA LB N = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (N - 1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (N - 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Figure 7.12 shows an example of the setting procedure for normal mode. Rev. 3.00 Mar 17, 2006 page 302 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Normal mode setting [1] Set each bit in DMABCRH. * Set the FAE bit to 1 to select full address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACRA and DMACRB. * Set the transfer data size with the DTSZ bit. * Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. * Clear the BLKE bit to 0 to select normal mode. * Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. * Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode Figure 7.12 Example of Normal Mode Setting Procedure Rev. 3.00 Mar 17, 2006 page 303 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 0 0 Function Source address register Destination address register Holds block size Block size counter Initial Setting Start address of transfer source Start address of transfer destination Block size Operation Incremented/decremented every transfer, or fixed Incremented/decremented every transfer, or fixed Fixed 7 0 ETCRAH Block size 7 ETCRAL 15 ETCRB 0 Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 0 Block transfer counter Number of block transfers MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area. Rev. 3.00 Mar 17, 2006 page 304 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where: TA TB BA BB LA LB N M = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (M*N - 1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (N - 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area. Rev. 3.00 Mar 17, 2006 page 305 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend: Address Address Address Address Where: TA TB BA BB LA LB N M = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (N - 1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (M*N - 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. Rev. 3.00 Mar 17, 2006 page 306 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE*(-1)SAID*2DTSZ Write to address specified by MARB MARB = MARB + DAIDE*(-1)DAID *2DTSZ ETCRAL = ETCRAL - 1 No ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 No Yes MARB = MARB - DAIDE*(-1)DAID*2DTSZ*ETCRAH MARA = MARA - SAIDE*(-1)SAID*2DTSZ*ETCRAH ETCRB = ETCRB - 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7.15 Operation Flow in Block Transfer Mode Rev. 3.00 Mar 17, 2006 page 307 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. Block transfer mode setting [1] Set each bit in DMABCRH. * Set the FAE bit to 1 to select full address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. * Set the transfer data size with the DTSZ bit. * Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. * Set the BLKE bit to 1 to select block transfer mode. * Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. * Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. * Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Block transfer mode [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. * Set both the DTME bit and the DTE bit to 1 to enable transfer. Figure 7.16 Example of Block Transfer Mode Setting Procedure Rev. 3.00 Mar 17, 2006 page 308 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. CPU cycle T1 DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Source address Destination address Address bus RD HWR LWR Figure 7.17 Example of DMA Transfer Bus Timing Rev. 3.00 Mar 17, 2006 page 309 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.9 DMA Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle. Rev. 3.00 Mar 17, 2006 page 310 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one bus cycle is executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 3.00 Mar 17, 2006 page 311 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev. 3.00 Mar 17, 2006 page 312 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated during data transfer, block transfer operation is not affected until data transfer for one block has ended. DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge. Rev. 3.00 Mar 17, 2006 page 313 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bus release DREQ Address bus DMA control Channel DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle Request Minimum of 2 cycles [1] [2] [3] Request clear period Request Minimum of 2 cycles [4] [5] [6] Request clear period [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling edge. Rev. 3.00 Mar 17, 2006 page 314 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 1 block transfer Bus release DREQ Address bus DMA control Channel DMA read DMA write DMA Bus dead release DMA read 1 block transfer DMA write DMA dead Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle Request Request clear period Request Minimum of 2 cycles Request clear period Minimum of 2 cycles [1] [2] [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 3.00 Mar 17, 2006 page 315 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level. Bus release DREQ Address bus DMA control Channel Idle DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Read Write Idle Request Minimum of 2 cycles [1] [2] Request clear period Request Minimum of 2 cycles Request clear period [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level. Rev. 3.00 Mar 17, 2006 page 316 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 1 block transfer Bus release DREQ Address bus DMA control Channel DMA read DMA write DMA Bus dead release DMA read 1 block transfer DMA write DMA dead Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle Request Minimum of 2 cycles [1] [2] [3] Request clear period Request Minimum of 2 cycles [4] [5] [6] Request clear period [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 3.00 Mar 17, 2006 page 317 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.10 DMA Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA DMA read dead DMA read Address bus RD DACK TEND DMA read DMA read Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Rev. 3.00 Mar 17, 2006 page 318 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA dead DMA read DMA read DMA read Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.27 Example of Single Address Mode (Word Read) Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 3.00 Mar 17, 2006 page 319 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA DMA write dead DMA write DMA write DMA write Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.28 Example of Single Address Mode Transfer (Byte Write) Rev. 3.00 Mar 17, 2006 page 320 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA dead DMA write DMA write DMA write Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling edge. Rev. 3.00 Mar 17, 2006 page 321 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Bus release DREQ Address bus DACK DMA single Bus release DMA single Bus release Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Rev. 3.00 Mar 17, 2006 page 322 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level. Bus release Bus release DREQ DMA single Bus release DMA single Address bus DACK Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of , and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the Rev. 3.00 Mar 17, 2006 page 323 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.32 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead Internal address Internal read signal External address HWR, LWR TEND Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. Rev. 3.00 Mar 17, 2006 page 324 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) DMA read DMA single CPU read DMA single CPU read Internal address Internal read signal External address RD DACK Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.12 Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.11 summarizes the priority order for DMAC channels. Table 7.11 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the Rev. 3.00 Mar 17, 2006 page 325 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA DMA write read DMA read Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write DMA write DMA read DMA write DMA read Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 7.34 Example of Multi-Channel Transfer 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or external bus release cycle may arise. In this case, the bus controller will suspend the transfer and insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed until the DMAC releases the external bus.) When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after an external write cycle. The external read cycle and external write cycle are inseparable, and so the bus cannot be released between these two cycles. When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus release cycle. Rev. 3.00 Mar 17, 2006 page 326 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL. Write 1 to the DTME bit. DTE = 1 DTME = 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt 7.5.15 Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software. Rev. 3.00 Mar 17, 2006 page 327 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) Forced termination of DMAC [1] Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 [1] Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [1] [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Clearing full address mode Stop the channel Initialize DMACR [2] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7.37 Example of Procedure for Clearing Full Address Mode Rev. 3.00 Mar 17, 2006 page 328 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.12 Interrupt Sources and Priority Order Interrupt Source Interrupt Name DMTEND0A DMTEND0B DMTEND1A DMTEND1B Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12. Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while the DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev. 3.00 Mar 17, 2006 page 329 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.7 7.7.1 Usage Notes DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. * DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA transfer cycle DMA last transfer cycle DMA dead DMA read DMA Internal address DMA control DMA register operation Idle Transfer source Read Transfer destination Write DMA write DMA read DMA write Transfer source Idle Read Transfer destination Write Dead Idle [1] [2] [1] [2'] [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2'] Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Note: In single address transfer mode, the update timing is the same as [1]. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 7.39 DMAC Register Update Timing Rev. 3.00 Mar 17, 2006 page 330 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) * If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. CPU longword read MAR upper word read DMA internal address DMA control DMA register operation Idle Transfer source Read Transfer destination Write MAR lower word read DMA transfer cycle DMA read DMA write Idle [1] [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.40 Contention between DMAC Register Update and CPU Read 7.7.2 Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. * Transfer end/break interrupt (DTE = 0 and DTIE = 1) * TEND pin enable (TEE = 1) * DACK pin enable (FAE = 0 and SAE = 1) 7.7.3 Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Rev. 3.00 Mar 17, 2006 page 331 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) * Write data buffer function and DMAC register setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. * Write data buffer function and DMAC operation timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. 7.7.4 TEND Output If the last transfer cycle is for an internal address, note that even if low-level output at the TEND pin has been set, a low level may not be output at the TEND pin under the following external bus conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed in parallel. 1. EXDMAC cycle 2. Write cycle with write buffer mode enabled 3. DMAC single address cycle for a different channel with write buffer mode enabled 4. Bus release cycle 5. CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in synchronization with the bus cycle. However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in this case for the refresh cycle. Rev. 3.00 Mar 17, 2006 page 332 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) DMA read Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. DMA write Figure 7.41 Example in Which Low Level Is Not Output at TEND Pin 7.7.5 Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. Rev. 3.00 Mar 17, 2006 page 333 of 926 REJ09B0283-0300 Section 7 DMA Controller (DMAC) 7.7.6 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. 7.7.7 Internal Interrupt after End of Transfer When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if the DTA bit in DMABCRH is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if the DTA bit is set to 1. An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary. 7.7.8 Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write 1 to them. Rev. 3.00 Mar 17, 2006 page 334 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Section 8 EXDMA Controller This LSI has a built-in four-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. 8.1 Features * Direct specification of 16-Mbyte address space * Selection of byte or word transfer data length * Maximum number of transfers: 16M (16,777,215)/infinite (free-running) * Selection of dual address mode or single address mode * Selection of cycle steal mode or burst mode as bus mode * Selection of normal mode or block transfer mode as transfer mode * Two kinds of transfer requests: external request and auto-request * An interrupt request can be sent to the CPU at the end of the specified number of transfers. * Repeat area designation function: * Operation in parallel with internal bus master: * Acceptance of a transfer request and the start of transfer processing can be reported to an external device via the EDRAK pin. * Module stop mode can be set. Figure 8.1 shows a block diagram of the EXDMAC. EDMA260A_010020020400 Rev. 3.00 Mar 17, 2006 page 335 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bus controller Data buffer External pins EDREQ EDRAK ETEND EDACK Interrupt request signals to CPU for individual channels Control logic Address buffer Processor EDSAR EDDAR EDMDR EDACR EDTCR Internal data bus Legend: EDSAR: EDDAR: EDTCR: EDMDR: EDACR: EXDMA source address register EXDMA destination address register EXDMA transfer count register EXDMA mode control register EXDMA address control register Figure 8.1 Block Diagram of EXDMAC Rev. 3.00 Mar 17, 2006 page 336 of 926 REJ09B0283-0300 Module data bus Section 8 EXDMA Controller 8.2 Input/Output Pins Table 8.1 shows the EXDMAC pin configuration. Table 8.1 Channel 0 Pin Configuration Name EXDMA transfer request 0 EXDMA transfer acknowledge 0 EXDMA transfer end 0 EDREQ0 acceptance acknowledge Abbreviation EDREQ0 EDACK0 ETEND0 EDRAK0 I/O Input Output Output Output Function Channel 0 external request Channel 0 single address transfer acknowledge Channel 0 transfer end Notification to external device of channel 0 external request acceptance and start of execution Channel 1 external request Channel 1 single address transfer acknowledge Channel 1 transfer end Notification to external device of channel 1 external request acceptance and start of execution Channel 2 external request Channel 2 single address transfer acknowledge Channel 2 transfer end Notification to external device of channel 2 external request acceptance and start of execution Channel 3 external request Channel 3 single address transfer acknowledge Channel 3 transfer end Notification to external device of channel 3 external request acceptance and start of execution 1 EXDMA transfer request 1 EXDMA transfer acknowledge 1 EXDMA transfer end 1 EDREQ1 acceptance acknowledge EDREQ1 EDACK1 ETEND1 EDRAK1 Input Output Output Output 2 EXDMA transfer request 2 EXDMA transfer acknowledge 2 EXDMA transfer end 2 EDREQ2 acceptance acknowledge EDREQ2 EDACK2 ETEND2 EDRAK2 Input Output Output Output 3 EXDMA transfer request 3 EXDMA transfer acknowledge 3 EXDMA transfer end 3 EDREQ3 acceptance acknowledge EDREQ3 EDACK3 ETEND3 EDRAK3 Input Output Output Output Rev. 3.00 Mar 17, 2006 page 337 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.3 Register Descriptions The EXDMAC has the following registers. * EXDMA source address register_0 (EDSAR_0) * EXDMA destination address register_0 (EDDAR_0) * EXDMA transfer count register_0 (EDTCR_0) * EXDMA mode control register_0 (EDMDR_0) * EXDMA address control register_0 (EDACR_0) * EXDMA source address register_1 (EDSAR_1) * EXDMA destination address register_1 (EDDAR_1) * EXDMA transfer count register_1 (EDTCR_1) * EXDMA mode control register_1 (EDMDR_1) * EXDMA address control register_1 (EDACR_1) * EXDMA source address register_2 (EDSAR_2) * EXDMA destination address register_2 (EDDAR_2) * EXDMA transfer count register_2 (EDTCR_2) * EXDMA mode control register_2 (EDMDR_2) * EXDMA address control register_2 (EDACR_2) * EXDMA source address register_3 (EDSAR_3) * EXDMA destination address register_3 (EDDAR_3) * EXDMA transfer count register_3 (EDTCR_3) * EXDMA mode control register_3 (EDMDR_3) * EXDMA address control register_3 (EDACR_3) 8.3.1 EXDMA Source Address Register (EDSAR) EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR are undefined. Rev. 3.00 Mar 17, 2006 page 338 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.3.2 EXDMA Destination Address Register (EDDAR) EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when a device with DACK is specified as the transfer destination. The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR are undefined. 8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. Normal Transfer Mode: Bit 31 to 24 23 to 0 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. All 0 R/W 24-Bit Transfer Counter These bits specify the number of transfers. Setting H'000001 specifies one transfer. Setting H'000000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFFFF specifies the maximum number of transfers, that is 16,777,215. During EXDMA transfer, this counter shows the remaining number of transfers. This counter can be read at all times. When reading EDTCR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Rev. 3.00 Mar 17, 2006 page 339 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Block Transfer Mode: Bit 31 to 24 23 to 16 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256. The register value always indicates the specified block size. Undefined R/W 16-Bit Transfer Counter These bits specify the number of block transfers. Setting H'0001 specifies one block transfer. Setting H'0000 means no specification for the number of transfers, and the transfer counter function is halted. In this case, there is no transfer end interrupt by the transfer counter. Setting H'FFFF specifies the maximum number of block transfers, that is 65,535. During EXDMA transfer, this counter shows the remaining number of block transfers. 15 to 0 Rev. 3.00 Mar 17, 2006 page 340 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit 15 Bit Name EDA Initial Value 0 R/W R/(W) Description EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1. With external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. When this bit is cleared to 0 during an EXDMA operation, transfer is halted. If this bit is cleared to 0 during an EXDMA operation in block transfer mode, transfer processing is continued for the currently executing one-block transfer, and the bit is cleared on completion of the currently executing one-block transfer. If an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. Do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: Data transfer disabled on corresponding channel [Clearing conditions] * When the specified number of transfers end * When operation is halted by a repeat area overflow interrupt * When 0 is written to EDA while EDA = 1 (In block transfer mode, write is effective after end of one-block transfer) * Reset, NMI interrupt, hardware standby mode 1: Data transfer enabled on corresponding channel Note: The value written in the EDA bit may not be effective immediately. Rev. 3.00 Mar 17, 2006 page 341 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 14 Bit Name BEF Initial Value 0 R/W R/(W)* Description Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost. 0: No block transfer error [Clearing condition] Writing 0 to BEF after reading BEF = 1 1: Block transfer error [Setting condition] NMI interrupt during block transfer 13 EDRAKE 0 R/W EDRAK Pin Output Enable Enables output from the EDREQ acknowledge/execution start (EDRAK) pin. 0: EDRAK pin output disabled 1: EDRAK pin output enabled 12 ETENDE 0 R/W ETEND Pin Output Enable Enables output from the EXDMA transfer end (ETEND) pin. 0: ETEND pin output disabled 1: ETEND pin output enabled 11 EDREQS 0 R/W EDREQ Select Specifies low level sensing or falling edge sensing as the sampling method for the EDREQ pin used in external request mode. 0: Low level sensing (Low level sensing is used for the first transfer after transfer is enabled.) 1: Falling edge sensing Rev. 3.00 Mar 17, 2006 page 342 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 10 Bit Name AMS Initial Value 0 R/W R/W Description Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 8 MDS1 MDS0 0 0 R/W R/W Mode Select 1 and 0 These bits specify the activation source, bus mode, and transfer mode. 00: Auto request, cycle steal mode, normal transfer mode 01: Auto request, burst mode, normal transfer mode 10: External request, cycle steal mode, normal transfer mode 11: External request, cycle steal mode, block transfer mode 7 EDIE 0 R/W EXDMA Interrupt Enable Enables or disables interrupt requests. When this bit is set to 1, an interrupt is requested when the IRF bit is set to 1. The interrupt request is cleared by clearing this bit or the IRF bit to 0. 0: Interrupt request is not generated 1: Interrupt request is generated Rev. 3.00 Mar 17, 2006 page 343 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 6 Bit Name IRF Initial Value 0 R/W R/(W)* Description Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended. 0: No interrupt request [Clearing conditions] * * Writing 1 to the EDA bit Writing 0 to IRF after reading IRF = 1 1: Interrupt request occurrence [Setting conditions] * * * 5 TCEIE 0 R/W Transfer end interrupt request generated by transfer counter Source address repeat area overflow interrupt request Destination address repeat area overflow interrupt request Transfer Counter End Interrupt Enable Enables or disables transfer end interrupt requests by the transfer counter. When transfer ends according to the transfer counter while this bit is set to 1, the IRF bit is set to 1, indicating that an interrupt request has occurred. 0: Transfer end interrupt requests by transfer counter are disabled 1: Transfer end interrupt requests by transfer counter are enabled 4 SDIR 0 R/W Single Address Direction Specifies the data transfer direction in single address mode. In dual address mode, the specification by this bit is ignored. 0: Transfer direction: EDSAR external device with DACK 1: Transfer direction: External device with DACK EDDAR Rev. 3.00 Mar 17, 2006 page 344 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 3 Bit Name DTSIZE Initial Value 0 R/W R/W Description Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus mastership in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode. 0: Bus is not released 1: Bus is transferred if requested by an internal bus master 1, 0 -- All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. Note: * Only 0 can be written, to clear the flag. Rev. 3.00 Mar 17, 2006 page 345 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit 15 14 Bit Name SAT1 SAT0 Initial Value 0 0 R/W R/W R/W Description Source Address Update Mode These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored. 0X: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (-1 in byte transfer, -2 in word transfer) 13 SARIE 0 R/W Source Address Repeat Interrupt Enable When this bit is set to 1, in the event of source address repeat area overflow, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a source address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a source address repeat interrupt, transfer can be resumed from the state in which it ended. If a source address repeat area has not been designated, this bit is ignored. 0: Source address repeat interrupt is not requested 1: When source address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested Rev. 3.00 Mar 17, 2006 page 346 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 12 11 10 9 8 Bit Name SARA4 SARA3 SARA2 SARA1 SARA0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Source Address Repeat Area These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-oftwo number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the SARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11XXX: Setting prohibited Rev. 3.00 Mar 17, 2006 page 347 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 7 6 Bit Name DAT1 DAT0 Initial Value 0 0 R/W R/W R/W Description Destination Address Update Mode These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored. 0X: Fixed 10: Incremented (+1 in byte transfer, +2 in word transfer) 11: Decremented (-1 in byte transfer, -2 in word transfer) 5 DARIE 0 R/W Destination Address Repeat Interrupt Enable When this bit is set to 1, in the event of destination address repeat area overflow the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If the EDIE bit in EDMDR is 1 when the IRF bit in EDMDR is set to 1, an interrupt request is sent to the CPU. When used together with block transfer mode, a destination address repeat interrupt is requested at the end of a block-size transfer. If the EDA bit is set to 1 in EDMDR for the channel on which transfer is terminated by a destination address repeat interrupt, transfer can be resumed from the state in which it ended. If a destination address repeat area has not been designated, this bit is ignored. 0: Destination address repeat interrupt is not requested 1: When destination address repeat area overflow occurs, the IRF bit in EDMDR is set to 1 and an interrupt is requested Rev. 3.00 Mar 17, 2006 page 348 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Bit 4 3 2 1 0 Bit Name DARA4 DARA3 DARA2 DARA1 DARA0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Destination Address Repeat Area These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the repeat area in the case of address incrementing, or the last address of the repeat area in the case of address decrementing. If the DARIE bit is set to 1, an interrupt can be requested when repeat area overflow occurs. 00000: Not designated as repeat area 00001: Lower 1 bit (2-byte area) designated as repeat area 00010: Lower 2 bits (4-byte area) designated as repeat area 00011: Lower 3 bits (8-byte area) designated as repeat area 00100: Lower 4 bits (16-byte area) designated as repeat area : : 10011: Lower 19 bits (512-kbyte area) designated as repeat area 10100: Lower 20 bits (1-Mbyte area) designated as repeat area 10101: Lower 21 bits (2-Mbyte area) designated as repeat area 10110: Lower 22 bits (4-Mbyte area) designated as repeat area 10111: Lower 23 bits (8-Mbyte area) designated as repeat area 11XXX: Setting prohibited Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 349 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.4 8.4.1 Operation Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.2 EXDMAC Transfer Modes Transfer Mode Dual address mode Normal transfer mode Auto request mode * Burst/cycle steal mode External request mode * Cycle steal mode Block transfer mode External request mode * Burst transfer of specified block size for a single transfer request * Block size: 1 to 256 bytes or words Single address mode * Direct data transfer to/from external device using EDACK pin instead of source or destination address register * Above transfer mode can be specified in addition to address register setting * One transfer possible in one bus cycle (Transfer mode variations are the same as in dual address mode.) EDSAR/ EDACK EDACK/ EDDAR External request 1 to 65,535 or no specification Transfer Origin Auto request External request Number of Transfers Address Registers Source Destination EDDAR EDSAR 1 to 16,777,215 or no specification The transfer mode can be set independently for each channel. In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer request. With auto requests, burst or cycle steal transfer mode can be set. In burst transfer mode, continuous, high-speed transfer can be performed until the specified number of transfers have been executed or the transfer enable bit is cleared to 0. Rev. 3.00 Mar 17, 2006 page 350 of 926 REJ09B0283-0300 Section 8 EXDMA Controller In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the "no specification" setting (EDTCR = H'000000) is made for the number of transfers, the transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be performed endlessly. Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged, can be specified independently for each address register. In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of bytes. 8.4.2 Address Modes Dual Address Mode: In dual address mode, both the transfer source and transfer destination are specified by registers in the EXDMAC, and one transfer is executed in two bus cycles. The transfer source address is set in the source address register (EDSAR), and the transfer destination address is set in the transfer destination address register (EDDAR). In a transfer operation, the value in external memory specified by the transfer source address is read in the first bus cycle, and is written to the external memory specified by the transfer destination address in the next bus cycle. These consecutive read and write cycles are indivisible: another bus cycle (external access by an internal bus master, refresh cycle, or external bus release cycle) does not occur between these two cycles. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for two consecutive bus cycles. The EDACK signal is not output. Figure 8.2 shows an example of the timing in dual address mode. Rev. 3.00 Mar 17, 2006 page 351 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EXDMA read cycle Address bus RD WR ETEND EDSAR EXDMA write cycle EDDAR Figure 8.2 Example of Timing in Dual Address Mode Single Address Mode: In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory. In this mode, the EXDMAC accesses the transfer source or transfer destination external device by outputting the external I/O strobe signal (EDACK), and at the same time accesses the other external device in the transfer by outputting an address. In this way, DMA transfer can be executed in one bus cycle. In the example of transfer between external memory and an external device with DACK shown in figure 8.3, data is output to the data bus by the external device and written to external memory in the same bus cycle. The transfer direction, that is whether the external device with DACK is the transfer source or transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the external device with DACK to the external memory (EDDAR) when SDIR = 1. The setting in the source or destination address register not used in the transfer is ignored. The EDACK pin becomes valid automatically when single address mode is selected. The EDACK pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for one bus cycle. Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the timing. Rev. 3.00 Mar 17, 2006 page 352 of 926 REJ09B0283-0300 Section 8 EXDMA Controller External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode Rev. 3.00 Mar 17, 2006 page 353 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Transfer from external memory to external device with DACK EXDMA cycle Address bus RD WR EDACK Data bus ETEND Data output from external memory EDSAR Address to external memory space RD signal to external memory space Transfer from external device with DACK to external memory EXDMA cycle Address bus RD WR EDACK Data bus ETEND Data output from external device with DACK WR signal to external memory space EDDAR Address to external memory space Figure 8.4 Example of Timing in Single Address Mode Rev. 3.00 Mar 17, 2006 page 354 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.4.3 DMA Transfer Requests Auto Request Mode: In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR. In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode. Block transfer mode cannot be used. External Request Mode: In external request mode, transfer is started by a transfer request signal (EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while DMA transfer is enabled (EDA = 1). The transfer request source need not be the data transfer source or data transfer destination. The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level sensing when EDREQS = 0, falling edge sensing when EDREQS = 1). Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer processing has been started in response to a single external request. The EDRAK signal enables the external device to determine the timing of EDREQ signal negation, and makes it possible to provide handshaking between the transfer request source and the EXDMAC. In external request mode, block transfer mode can be used instead of burst mode. Block transfer mode allows continuous execution (burst operation) of the specified number of transfers (the block size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block unit. 8.4.4 Bus Modes There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto request, either cycle steal mode or burst mode can be selected. When the activation source is an external request, cycle steal mode is used. Cycle Steal Mode: In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC Rev. 3.00 Mar 17, 2006 page 355 of 926 REJ09B0283-0300 Section 8 EXDMA Controller takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted. For details on the operation when there are requests for a number of channels, see section 8.4.8, Channel Priority Order. Figure 8.5 shows an example of the timing in cycle steal mode. EDREQ EDRAK Bus cycle CPU CPU EXDMAC CPU CPU EXDMAC Bus returned temporarily to CPU Transfer conditions: * Single address mode, normal transfer mode * EDREQ low level sensing * CPU internal bus master is operating in external space Figure 8.5 Example of Timing in Cycle Steal Mode Burst Mode: In burst mode, once the EXDMAC acquires the bus it continues transferring data, without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external request mode. In burst mode, once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority. When the burst mode channel finishes its transfer, it releases the bus in the next cycle in the same way as in cycle steal mode. When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared to 0. If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is terminated. Rev. 3.00 Mar 17, 2006 page 356 of 926 REJ09B0283-0300 Section 8 EXDMA Controller When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus mastership during burst transfer. If there is no bus request, burst transfer is executed even if the BGUP bit is set to 1. Figure 8.6 shows examples of the timing in burst mode. Bus cycle CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU CPU cycle not generated Transfer conditions: Auto request mode, BGUP = 0 Bus cycle CPU EXDMAC CPU EXDMAC CPU EXDMAC CPU EXDMAC operates alternately with CPU Transfer conditions: Auto request mode, BGUP = 1 Figure 8.6 Examples of Timing in Burst Mode 8.4.5 Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode. When the activation source is an external request, either normal transfer mode or block transfer mode can be selected. When the activation source is an auto request, normal transfer mode is used. Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in response to one transfer request. EDTCR functions as a 24-bit transfer counter. The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each time a transfer request is accepted and transfer processing is started. Figure 8.7 shows examples of DMA transfer timing in normal transfer mode. Rev. 3.00 Mar 17, 2006 page 357 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EXDMA transfer cycle Bus cycle ETEND Transfer conditions: Dual address mode, auto request mode Read Write Last EXDMA transfer cycle Read Write EDREQ EDRAK Bus cycle EDACK Transfer conditions: Single address mode, external request mode EXDMA EXDMA Figure 8.7 Examples of Timing in Normal Transfer Mode Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During transfer of a block, transfer requests for other higher-priority channels are held pending. When transfer of one block is completed, the bus is released in the next cycle. When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another bus mastership during block transfer. Address register values are updated in the same way as in normal mode. There is no function for restoring the initial address register values after each block transfer. The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block ends. The EDRAK signal is output once for one transfer request (for transfer of one block). Rev. 3.00 Mar 17, 2006 page 358 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Caution is required when setting the repeat area overflow interrupt of the repeat area function in block transfer mode. See section 8.4.6, Repeat Area Function, for details. Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode. EDREQ EDRAK One-block transfer cycle Bus cycle CPU CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU cycle not generated ETEND Transfer conditions: * Single address mode * BGUP = 0 * Block size (EDTCR[23:16]) = 3 Figure 8.8 Example of Timing in Block Transfer Mode 8.4.6 Repeat Area Function The EXDMAC has a function for designating a repeat area for source addresses and/or destination addresses. When a repeat area is designated, the address register values repeat within the range specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if the repeat area function is used, the operation that restores the address register value to the buffer start address is performed automatically within the EXDMAC. The repeat area function can be set independently for the source address register and the destination address register. Rev. 3.00 Mar 17, 2006 page 359 of 926 REJ09B0283-0300 Section 8 EXDMA Controller The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat area can be specified independently. When the address register value is the last address in the repeat area and repeat area overflow occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1 in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register. If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9 illustrates the operation of the repeat area function. When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3) External memory : H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 : H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Repeat area overflow interrupt can be requested Repeated Range of EDSAR values Figure 8.9 Example of Repeat Area Function Operation Caution is required when the repeat area overflow interrupt function is used together with block transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer Rev. 3.00 Mar 17, 2006 page 360 of 926 REJ09B0283-0300 Section 8 EXDMA Controller mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the repeat area range. If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.10 shows an example in which block transfer mode is used together with the repeat area function. When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23-16] = 5) is set in block transfer mode External memory : H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 : H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Block transfer in progress H'240000 H'240001 Interrupt requested Range of EDSAR values First block transfer Second block transfer Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode 8.4.7 Registers during DMA Transfer Operation EXDMAC register values are updated as DMA transfer processing is performed. The updated values depend on various settings and the transfer status. The following registers and bits are updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR, EXDMA Source Address Register (EDSAR): When the EDSAR address is accessed as the transfer source, after the EDSAR value is output, EDSAR is updated with the address to be Rev. 3.00 Mar 17, 2006 page 361 of 926 REJ09B0283-0300 Section 8 EXDMA Controller accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by 2. When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output. Do not write to EDSAR for a channel on which a transfer operation is in progress. EXDMA Destination Address Register (EDDAR): When the EDDAR address is accessed as the transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented when DAT1 = 1 and DAT0 = 1. The size of the increment or decrement is determined by the size of the data transferred. When the DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by 2. When a repeat area setting is made, the operation conforms to that setting. The upper part of the address set for the repeat area function is fixed, and is not affected by address updating. When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output. Do not write to EDDAR for a channel on which a transfer operation is in progress. Rev. 3.00 Mar 17, 2006 page 362 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EXDMA Transfer Count Register (EDTCR): When a DMA transfer is performed, the value in EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed. However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0] value does not change. In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read by the CPU during DMA transfer, a longword access must be used. During a transfer operation, EDTCR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDTCR value to ensure that the correct value is output. In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is contention between an address update associated with DMA transfer and a write by the CPU, the CPU write has priority. In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated. Transfer does not end if the CPU writes 0 to EDTCR. Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode. Rev. 3.00 Mar 17, 2006 page 363 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EDTCR in normal transfer mode Before update 23 EDTCR 23 EDTCR 1 to H'FFFFFF 0 0 -1 23 0 to H'FFFFFE 0 Fixed 23 0 0 After update 0 EDTCR in block transfer mode Before update 23 16 15 Block 0 size 23 16 15 Block 1 to H'FFFF size After update 23 16 15 Block 0 size 23 16 15 Block 0 to H'FFFE size 0 Fixed 0 EDTCR 0 -1 0 EDTCR Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and Block Transfer Mode EDA Bit in EDMDR: The EDA bit in EDMDR is written to by the CPU to control enabling and disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is not immediately effective. Conditions for EDA bit clearing by the EXDMAC include the following: * When the EDTCR value changes from 1 to 0, and transfer ends * When a repeat area overflow interrupt is requested, and transfer ends * When an NMI interrupt is generated, and transfer halts * A reset * Hardware standby mode * When 0 is written to the EDA bit, and transfer halts When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA transfer period. In block transfer mode, since a block-size transfer is carried out without interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current block-size transfer. Rev. 3.00 Mar 17, 2006 page 364 of 926 REJ09B0283-0300 Section 8 EXDMA Controller In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until the end of the last DMA cycle. Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that the EDA bit has been cleared to 0. Figure 8.12 shows the procedure for changing register settings in an operating channel. Changing register settings in operating channel Write 0 to EDA bit 1 1. Write 0 to the EDA bit in EDMDR. 2. Read the EDA bit. 3. Confirm that EDA = 0. If EDA = 1, this indicates that DMA transfer is in progress. 4. Write the required set values to the registers. Read EDA bit 2 EDA bit = 0? Yes Change register settings Register setting changes completed 3 No 4 Figure 8.12 Procedure for Changing Register Settings in Operating Channel BEF Bit in EDMDR: In block transfer mode, the specified number of transfers (equivalent to the block size) is performed in response to a single transfer request. To ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt. If an NMI interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1. Rev. 3.00 Mar 17, 2006 page 365 of 926 REJ09B0283-0300 Section 8 EXDMA Controller IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer ends following the end of the DMA transfer bus cycle in which the source generating the interrupt occurred. If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is automatically cleared to 0 and the interrupt request is cleared. For details on interrupts, see section 8.5, Interrupts Sources. 8.4.8 Channel Priority Order The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3. Table 8.3 shows the EXDMAC channel priority order. Table 8.3 Channel Channel 0 Channel 1 Channel 2 Channel 3 Low EXDMAC Channel Priority Order Priority High If transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order in table 8.3 is selected for transfer. Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode): If transfer requests for different channels are issued during a transfer operation, the highest-priority channel (excluding the currently transferring channel) is selected. The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus mastership other than the EXDMAC at this time, a cycle for the other bus mastership is initiated. If there is no other bus request, the bus is released for one cycle. Channels are not switched during burst transfer or transfer of a block in block transfer mode. Figure 8.13 shows an example of the transfer timing when transfer requests occur simultaneously for channels 0, 1, and 2. The example in the figure is for external request cycle steal mode. Rev. 3.00 Mar 17, 2006 page 366 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Channel 0 transfer Channel 0 Bus release Channel 1 transfer Channel 2 transfer Address bus Channel 1 Bus release Channel 2 EXDMA control Idle Channel 0 Channel 1 Channel 2 Channel 0 Request cleared Channel 1 Request Selected held Request cleared Channel 2 Not Request Request selected held held Selected Request cleared Figure 8.13 Example of Channel Priority Timing Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode: If transfer requests for different channels are issued during a transfer in auto request cycle steal mode, the operation depends on the channel priority. If the channel that made the transfer request is of higher priority than the channel currently performing transfer, the channel that made the transfer request is selected. If the channel that made the transfer request is of lower priority than the channel currently performing transfer, that channel's transfer request is held pending, and the currently transferring channel remains selected. The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus mastership other than the EXDMAC at this time, a cycle for the other bus mastership is initiated. If there is no other bus request, the bus is released for one cycle. Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode. Rev. 3.00 Mar 17, 2006 page 367 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Conditions (1) Channel 0: Auto request, cycle steal mode Channel 1: External request, cycle steal mode, low level activation Bus Channel 0 * Channel 0 * Channel 0 * Channel 1 * Channel 1 * Channel 0 EDA bit Channel 1/ EDREQ1 pin Conditions (2) Channel 1: External request, cycle steal mode, low level activation Channel 2: Auto request, cycle steal mode Bus Channel 2 * Channel 2 * Channel 1 * Channel 2 * Channel 1 * Channel 1 Channel 1/ EDREQ1 pin Channel 2 EDA bit Conditions (3) Channel 0: Auto request, cycle steal mode Channel 2: Auto request, cycle steal mode Bus Channel 2 * Channel 2 * Channel 0 * Channel 0 * Channel 2 * Channel 0 EDA bit Channel 2 EDA bit Note: *: Bus release Figure 8.14 Examples of Channel Priority Timing Rev. 3.00 Mar 17, 2006 page 368 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.4.9 EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. DMA read DMA write Address bus RD HWR LWR ETEND Bus release Bus release Bus release Last transfer cycle Bus release DMA read DMA write DMA read DMA write Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer Rev. 3.00 Mar 17, 2006 page 369 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Normal Transfer Mode (Burst Mode): Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends. Once burst transfer starts, requests from other channels, even of higher priority, are held pending until transfer ends. DMA read DMA write DMA read DMA write DMA read DMA write Address bus RD HWR LWR ETEND Bus release Last transfer cycle Burst transfer Bus release Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer If an NMI interrupt is generated while a channel designated for burst transfer is enabled for transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been initiated within the EXDMAC, the bus is released on completion of the currently executing byte or word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared. Rev. 3.00 Mar 17, 2006 page 370 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Block Transfer Mode (Cycle Steal Mode): Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. DMA read Address bus RD HWR LWR ETEND Bus release Block transfer Bus release Last block transfer Bus release DMA write DMA read DMA write DMA read DMA write DMA read DMA write Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer Rev. 3.00 Mar 17, 2006 page 371 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EDREQ Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge. Bus release EDREQ Address bus DMA control Channel Idle Request [1] [2] Transfer source Transfer destination Transfer source Transfer destination DMA read DMA write Bus release DMA read DMA write Bus release Read Write Idle Request [4] Acceptance resumed [5] Read Write Idle Request clearance period Request clearance period Minimum 3 cycles [3] Minimum 3 cycles [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of . When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of o, and request is held.) Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling edge. Rev. 3.00 Mar 17, 2006 page 372 of 926 REJ09B0283-0300 Section 8 EXDMA Controller One block transfer Bus release EDREQ Address bus DMA control Idle Channel Request [1] [2] Transfer source Transfer destination One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Transfer source Transfer destination Read Write Idle Request [4] Acceptance resumed [5] Read Write Idle Request clearance period Request clearance period Minimum 3 cycles [3] Minimum 3 cycles [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of . When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 3.00 Mar 17, 2006 page 373 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EDREQ Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level. Bus release EDREQ Address bus DMA control Idle Channel Transfer source Transfer destination Transfer source Transfer destination DMA read DMA write Bus release DMA read DMA write Bus release Read Write Idle Read Write Idle Request clearance period Request Minimum 3 cycles [1] [2] [3] Request clearance period Request Minimum 3 cycles [4] [5] [6] [7] Acceptance resumed Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low level. Rev. 3.00 Mar 17, 2006 page 374 of 926 REJ09B0283-0300 Section 8 EXDMA Controller One block transfer Bus release EDREQ Address bus DMA control Channel Idle Request [1] [2] Transfer source Transfer destination One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Transfer source Transfer destination Read Write Idle Request [4] Acceptance resumed [5] Read Write Idle Request clearance period Request clearance period Minimum 3 cycles [3] Minimum 3 cycles [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of dead cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 3.00 Mar 17, 2006 page 375 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.4.10 EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2state access space to an external device. DMA read Address bus RD EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle DMA read DMA read DMA read Figure 8.22 Example of Single Address Mode (Byte Read) Transfer Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read Address bus RD EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release DMA read DMA read Figure 8.23 Example of Single Address Mode (Word Read) Transfer After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Rev. 3.00 Mar 17, 2006 page 376 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Single Address Mode (Write): Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Bus release Last Bus release transfer cycle DMA write DMA write DMA write Figure 8.24 Example of Single Address Mode (Byte Write) Transfer Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release DMA write DMA write Figure 8.25 Example of Single Address Mode (Word Write) Transfer Rev. 3.00 Mar 17, 2006 page 377 of 926 REJ09B0283-0300 Section 8 EXDMA Controller After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. EDREQ Pin Falling Edge Activation Timing: Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge. Bus release EDREQ Address bus EDACK DMA control Channel Idle Request Single Transfer source/ destination Transfer source/ destination DMA single Bus release DMA single Bus release Idle Request Single Idle Request clearance period Request clearance period Minimum 3 cycles [1] [2] [3] Minimum 3 cycles [4] Acceptance resumed [5] [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle start; EDREQ pin high level sampling is started at rise of . When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ Pin Falling Edge EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the DMA single cycle, acceptance resumes after the end of the single cycle, and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 3.00 Mar 17, 2006 page 378 of 926 REJ09B0283-0300 Section 8 EXDMA Controller EDREQ Pin Low Level Activation Timing: Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level. Bus release EDREQ Address bus EDACK DMA control Channel Idle Request Single Transfer source/ destination Transfer source/ destination DMA single Bus release DMA single Bus release Idle Request Single Idle Request clearance period Request clearance period Minimum 3 cycles [1] [2] [3] Minimum 3 cycles [4] Acceptance resumed [5] [6] [7] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. DMA cycle is started. Acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of , and request is held.) Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the EDMDR write cycle for setting the transfer-enabled state. When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low level sampling is performed again; this sequence of operations is repeated until the end of the transfer. Rev. 3.00 Mar 17, 2006 page 379 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.4.11 Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a onecycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. Figures 8.28 to 8.30 show operation timing examples for various conditions. pin 3 cycles EXDMA read EXDMA write Bus release CPU operation EDA = 1 write Internal bus space cycles 1 cycle EXDMA read EXDMA write Bus release Last transfer cycle EXDMA read EXDMA write Bus cycle Bus release ETEND EDA bit 0 1 0 Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode) Rev. 3.00 Mar 17, 2006 page 380 of 926 REJ09B0283-0300 Section 8 EXDMA Controller pin 1 bus cycle CPU cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle CPU cycle Last transfer cycle EXDMA single transfer cycle CPU cycle Bus cycle CPU operation External space External space External space External space EDACK ETEND Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode) pin 1 cycle EXDMA single cycle Bus release Current channel EDACK EXDMA single cycle Bus release 1 cycle EXDMA single cycle Bus release 1 cycle EXDMA single cycle Bus release Bus release Bus cycle Higher-priority channel EXDMA cycle Other channel transfer request (EDREQ) Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Rev. 3.00 Mar 17, 2006 page 381 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 8.31 to 8.34 show operation timing examples for various conditions. pin Last transfer cycle Bus cycle CPU cycle CPU cycle EXDMA read EXDMA write EXDMA read EXDMA write Repeated EXDMA read EXDMA write CPU cycle CPU operation External space External space External space ETEND EDA bit 1 0 Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 0) pin 1 bus cycle EXDMA read EXDMA write EXDMA read EXDMA write 1 bus cycle EXDMA read EXDMA write Bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU operation External space External space External space External space Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Dual Address Mode/BGUP = 1) Rev. 3.00 Mar 17, 2006 page 382 of 926 REJ09B0283-0300 Section 8 EXDMA Controller pin 1 bus cycle Last transfer cycle Bus cycle EXDMA EXDMA EXDMA EXDMA EXDMA CPU cycle CPU cycle single cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle CPU operation External space External space External space External space External space EDACK ETEND Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/BGUP = 1) pin Last transfer cycle Bus cycle Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Bus release Original channel EDACK 1 cycle Bus release Other channel EXDMA cycle Original channel ETEND Other channel transfer request (EDREQ) Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Rev. 3.00 Mar 17, 2006 page 383 of 926 REJ09B0283-0300 Section 8 EXDMA Controller External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.35 to 8.38 show operation timing examples for various conditions. pin EDREQ EDRAK 3 cycles Bus cycle Bus release EXDMA read EXDMA write Bus release Last transfer cycle EXDMA read EXDMA write Bus release ETEND EDA bit 1 0 Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing) Rev. 3.00 Mar 17, 2006 page 384 of 926 REJ09B0283-0300 Section 8 EXDMA Controller pin EDREQ EDRAK 2 bus cycles Bus cycle CPU cycle CPU cycle CPU cycle EXDMA single transfer cycle CPU cycle CPU cycle Last transfer cycle EXDMA single transfer cycle CPU cycle CPU operation External space External space External space External space External space External space EDACK ETEND Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing) pin EDREQ EDRAK EDREQ acceptance internal processing state Bus cycle Edge confirmation Start of transfer processing Start of high level sensing Edge confirmation Start of transfer processing Start of high level sensing Edge confirmation Start of transfer processing Start of high level sensing Bus release EXDMA single transfer cycle Bus release EXDMA single transfer cycle Bus release EXDMA single transfer cycle EDACK Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing) Rev. 3.00 Mar 17, 2006 page 385 of 926 REJ09B0283-0300 Section 8 EXDMA Controller pin Original channel EDREQ Original channel EDRAK 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK 1 cycle Other channel transfer cycle Bus release 1 cycle EXDMA read EXDMA write Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing External Request/Cycle Steal Mode/Block Transfer Mode: In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.39 to 8.44 show operation timing examples for various conditions. Rev. 3.00 Mar 17, 2006 page 386 of 926 REJ09B0283-0300 pin EDREQ EDRAK 1-block-size transfer period Last transfer in block EXDMA read Repeated EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write 3 cycles Bus release EXDMA read EXDMA write Last block Last transfer cycle EXDMA read Repeated EXDMA write Bus release Bus cycle Bus release ETEND Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) Rev. 3.00 Mar 17, 2006 page 387 of 926 REJ09B0283-0300 EDA bit 1 0 Section 8 EXDMA Controller Section 8 EXDMA Controller pin Rev. 3.00 Mar 17, 2006 page 388 of 926 REJ09B0283-0300 1-block-size transfer period Last transfer in block EXDMA single transfer cycle Repeated EXDMA single transfer cycle EXDMA single transfer cycle 3 cycles Bus release EXDMA single transfer cycle Last block Last transfer cycle EXDMA single transfer cycle Repeated Bus release EDREQ EDRAK Bus cycle Bus release EDACK Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) ETEND pin EDREQ EDRAK 1-block-size transfer period Last transfer in block 2 bus cycles CPU cycle CPU cycle EXDMA single transfer cycle CPU cycle Repeated External space External space External space External space External space CPU cycle EXDMA single transfer cycle EXDMA single transfer cycle 1-block-size transfer period Last transfer in block EXDMA single transfer cycle Repeated CPU cycle Bus cycle CPU cycle CPU operation External space EDACK Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) Rev. 3.00 Mar 17, 2006 page 389 of 926 REJ09B0283-0300 Section 8 EXDMA Controller ETEND Section 8 EXDMA Controller pin Rev. 3.00 Mar 17, 2006 page 390 of 926 REJ09B0283-0300 1-block-size transfer period 1 bus cycle CPU cycle EXDMA read EXDMA write EXDMA read EXDMA write CPU cycle CPU cycle CPU cycle 1 bus cycle EXDMA read Repeated External space External space External space External space External space External space External space 1 bus cycle CPU cycle Last transfer in block EXDMA read EXDMA write CPU cycle CPU cycle EDREQ EDRAK Bus cycle CPU cycle CPU operation External space Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) ETEND pin EDREQ EDRAK 1-block-size transfer period 1 bus cycle CPU cycle EXDMA EXDMA transfer cycle transfer cycle EXDMA EXDMA transfer cycle transfer cycle 1 bus cycle 1 bus cycle Last transfer in block EXDMA transfer cycle Bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle Repeated EXDMA EXDMA transfer cycle transfer cycle CPU cycle CPU cycle CPU operation External space External space External space External space External space External space External space External space EDACK Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) Rev. 3.00 Mar 17, 2006 page 391 of 926 REJ09B0283-0300 Section 8 EXDMA Controller ETEND Section 8 EXDMA Controller pin EDREQ Rev. 3.00 Mar 17, 2006 page 392 of 926 REJ09B0283-0300 1-block-size transfer period Last transfer in block EXDMA read Repeated Bus release EXDMA write EXDMA read EXDMA write Other channel EXDMA cycle EXDMA read Bus release EXDMA write 1-block-size transfer period Last transfer in block EXDMA read Repeated EXDMA write EDRAK Bus cycle Bus release ETEND Other channel EDREQ Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) Other channel EDRAK Section 8 EXDMA Controller 8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. Transfer End by 1 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this time, a transfer end interrupt request is generated by the transfer counter and the IRF bit in EDMDR is set to 1. In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes from 1 to 0. DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer. Transfer End by Repeat Area Overflow Interrupt: If an address overflows the repeat area when a repeat area specification has been made and repeat interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit in EDMDR is set to 1. In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. Transfer end by means of a repeat area overflow interrupt occurs between block-size transfers. Transfer End by 0-Write to EDA Bit in EDMDR: When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of the DMA cycle in which transfer is in progress or a transfer request was accepted. In block transfer mode, DMA transfer halts after completion of one-block-size transfer. The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that point, the value of the EDA bit will be read as 1. Transfer Abort by NMI Interrupt: DMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is performed for all transfer requests for which EDRAK has been output. In dual address mode, processing is executed for the write cycle following the read cycle. Rev. 3.00 Mar 17, 2006 page 393 of 926 REJ09B0283-0300 Section 8 EXDMA Controller In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the block transfer was not carried out normally. When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit is 1 in EDMDR, transfer can be resumed from midway through a block. Hardware Standby Mode and Reset Input: The EXDMAC is initialized in hardware standby mode and by a reset. DMA transfer is not guaranteed in these cases. 8.4.13 Relationship between EXDMAC and Other Bus Masters The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external bus release cycle, or internal bus mastership (CPU, DTC, or DMAC) external space access cycle never occurs between the two. When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or external bus release state may be inserted after the write cycle. As the internal bus masters are of lower priority than the EXDMAC, external space accesses by internal bus masters are not executed until the EXDMAC releases the bus. The EXDMAC releases the bus in the following cases: 1. When DMA transfer is performed in cycle steal mode 2. When switching to a different channel 3. When transfer ends in burst transfer mode 4. When transfer of one block ends in block transfer mode 5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1 (however, the bus is not released between read and write cycles) Rev. 3.00 Mar 17, 2006 page 394 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.5 Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.4 Interrupt EXDMTEND0 Interrupt Sources and Priority Order Interrupt source Transfer end indicated by channel 0 transfer counter Channel 0 source address repeat area overflow Channel 0 destination address repeat area overflow Interrupt Priority High EXDMTEND1 Transfer end indicated by channel 1 transfer counter Channel 1 source address repeat area overflow Channel 1 destination address repeat area overflow EXDMTEND2 Transfer end indicated by channel 2 transfer counter Channel 2 source address repeat area overflow Channel 2 destination address repeat area overflow EXDMTEND3 Transfer end indicated by channel 3 transfer counter Channel 3 source address repeat area overflow Channel 3 destination address repeat area overflow Low Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant channel, and can be sent to the interrupt controller independently. The relative priority order of the channels is determined by the interrupt controller (see table 8.4). Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR. IRF bit Transfer end interrupt EDIE bit Figure 8.45 Transfer End Interrupt Logic Rev. 3.00 Mar 17, 2006 page 395 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt sources indiscriminately. The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46. Rev. 3.00 Mar 17, 2006 page 396 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Transfer end interrupt exception handling routine Transfer continuation processing Change register settings Write 1 to EDA bit End of interrupt handling routine (RTE instruction execution) [1] [2] Transfer restart after end of interrupt handling routine Clear IRF bit to 0 End of interrupt handling routine Change register settings [4] [5] [3] [6] Write 1 to EDA bit End of transfer restart processing [7] End of transfer restart processing [1] Write set values to the registers (transfer counter, address registers, etc.). [2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared. [3] The interrupt handling routine is ended with an RTE instruction, etc. [4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0. [5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is cleared. [6] Write set values to the registers (transfer counter, address registers, etc.). [7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer End Interrupt Occurred Rev. 3.00 Mar 17, 2006 page 397 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.6 8.6.1 Usage Notes EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. 8.6.2 Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being requested. Before setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in EDMDR to 0. When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following EXDMAC register settings remain valid in the module stop state, and so should be changed, if necessary, before making the module stop transition. * ETENDE = 1 in EDMDR (ETEND pin enable) * EDRAKE = 1 in EDMDR (EDRAK pin enable) * AMS = 1 in EDMDR (EDACK pin enable) 8.6.3 EDREQ Pin Falling Edge Activation Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal operations, as indicated below. [1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2]. [2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3]. [3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1]. After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used for the initial activation after transfer is enabled. Rev. 3.00 Mar 17, 2006 page 398 of 926 REJ09B0283-0300 Section 8 EXDMA Controller 8.6.4 Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state. When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the EDREQ pin from the previous end of transfer, etc. 8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1. 8.6.6 ETEND Pin and CBR Refresh Cycle If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may also go low in this case for the refresh cycle. Rev. 3.00 Mar 17, 2006 page 399 of 926 REJ09B0283-0300 Section 8 EXDMA Controller Rev. 3.00 Mar 17, 2006 page 400 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. 9.1 Features * Transfer possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes available * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 16-Mbyte address space possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set DTCH804A_010020020400 Rev. 3.00 Mar 17, 2006 page 401 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERG DTVECR DTC activation request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to G : DTC vector register Figure 9.1 Block Diagram of DTC 9.2 Register Descriptions DTC has the following registers. * DTC mode register A (MRA) * DTC mode register B (MRB) * DTC source address register (SAR) * DTC destination address register (DAR) * DTC transfer count register A (CRA) * DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in an on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. * DTC enable registers A to G (DTCERA to DTCERG) * DTC vector register (DTVECR) Rev. 3.00 Mar 17, 2006 page 402 of 926 REJ09B0283-0300 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERG DTVECR Section 9 Data Transfer Controller (DTC) 9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W -- -- Description Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined -- -- Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0x: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined -- -- DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined -- DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area Rev. 3.00 Mar 17, 2006 page 403 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Bit 0 Bit Name Sz Initial Value Undefined R/W -- Description DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer Legend: X: Don't care 9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit 7 Bit Name CHNE Initial Value Undefined R/W -- Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER is not performed. 6 DISEL Undefined -- DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends. 5 CHNS Undefined -- DTC Chain Transfer Select Specifies the chain transfer condition. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0 4 to 0 -- Undefined -- Reserved These bits have no effect on DTC operation, and should always be written with 0. Rev. 3.00 Mar 17, 2006 page 404 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 9.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 9.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. This register is not available in normal and repeat modes. 9.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) DTCER which is comprised of seven registers, DTCERA to DTCERG, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 9.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Rev. 3.00 Mar 17, 2006 page 405 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Bit 7 6 5 4 3 2 1 0 Bit Name DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions] * * When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended 9.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the bit SWDTE is 0, these bits can be written. Rev. 3.00 Mar 17, 2006 page 406 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 9.2 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip supporting module DTC DTVECR Interrupt controller Interrupt mask CPU Figure 9.2 Block Diagram of DTC Activation Source Control Rev. 3.00 Mar 17, 2006 page 407 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 9.3 and the register information start address should be located at the corresponding vector address to the activation source. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address. Note: Not available in this LSI. Lower addresses 0 Start address of register information MRA MRB CRA Chain transfer MRA MRB CRA Four bytes SAR DAR CRB Register information for second transfer in case of chain transfer 1 2 SAR DAR CRB Register information 3 Figure 9.3 Correspondence between DTC Vector Address and Register Information Rev. 3.00 Mar 17, 2006 page 408 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Table 9.1 Origin of Activation Source Software External pin Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Vector Number DTVECR 16 17 18 19 20 21 22 23 24 25 26 17 18 19 30 31 38 40 41 42 43 48 49 52 53 56 57 58 59 DTC Vector Address H'0400 + (DTVECR [6:0] x 2) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0430 H'0432 H'0434 H'0436 H'0438 H'043A H'043C H'043E H'044C H'0450 H'0452 H'0454 H'0456 H'0460 H'0462 H'0468 H'046A H'0470 H'0472 H'0474 H'0476 DTCE* -- DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 Priority High A/D TPU_0 ADI TGI0A TGI0B TGI0C TGI0D TPU_1 TPU_2 TPU_3 TGI1A TGI1B TGI2A TGI2B TGI3A TGI3B TGI3C TGI3D Low Rev. 3.00 Mar 17, 2006 page 409 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Origin of Activation Source TPU_4 TPU_5 TMR_0 TMR_1 DMAC Activation Source TGI4A TGI4B TGI5A TGI5B CMIA0 CMIB0 CMIA1 CMIB1 DMTEND0A DMTEND0B DMTEND1A DMTEND1B Vector Number 64 65 68 69 72 73 76 77 80 81 82 83 89 90 93 94 97 98 DTC Vector Address H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049A H'04A0 H'04A2 H'04A4 H'04A6 H'04B2 H'04B4 H'04BA H'04BC H'04C2 H'04C4 DTCE* DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 DTCEG7 DTCEG6 Priority High SCI_0 SCI_1 SCI_2 Note: * RXI0 TXI0 RXI1 TXI1 RXI2 TXI2 Low DTCE bits with no corresponding interrupt are reserved, and should be written with 0. When clearing the software standby state or all-module-clocks-stop mode with an interrupt, write 0 to the corresponding DTCE bit. 9.5 Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. There are three transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). A setting can also be made to have chain transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be performed by the DTC itself. Rev. 3.00 Mar 17, 2006 page 410 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Figure 9.4 shows a flowchart of DTC operation, and table 9.2 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? No Yes CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No No Yes Transfer counter = 0? No DISEL = 1? Yes No Yes Clear activation flag Clear DTCER End Interrupt exception handling Figure 9.4 Flowchart of DTC Operation Rev. 3.00 Mar 17, 2006 page 411 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Table 9.2 Chain Transfer Conditions 1st Transfer 2nd Transfer CR Not 0 0 -- -- CHNE -- -- -- 0 0 0 CHNS -- -- -- -- -- -- -- -- -- -- -- DISEL -- -- -- 0 0 1 -- 0 0 1 -- CR -- -- -- Not 0 0 -- -- Not 0 0 -- -- DTC Transfer Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Interrupt request to CPU CHNE 0 0 0 1 CHNS -- -- -- 0 DISEL 0 0 1 -- 1 1 1 1 0 -- Not 0 0 -- 0 0 0 1 1 1 Not 0 -- 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 9.3 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.3 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Function in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used Rev. 3.00 Mar 17, 2006 page 412 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) SAR Transfer DAR Figure 9.5 Memory Mapping in Normal Mode 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 9.4 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Function in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used Rev. 3.00 Mar 17, 2006 page 413 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) SAR or DAR Repeat area Transfer DAR or SAR Figure 9.6 Memory Mapping in Repeat Mode 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.5 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt is requested. Table 9.5 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Function in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Designates transfer count Rev. 3.00 Mar 17, 2006 page 414 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 9.7 Memory Mapping in Block Transfer Mode 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.8 shows the operation of chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is 1, the next register information, which is located consecutively, is read and transfer is performed. This operation is repeated until the end of data transfer of register information with CHNE = 0. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Rev. 3.00 Mar 17, 2006 page 415 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 9.8 Operation of Chain Transfer 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. Rev. 3.00 Mar 17, 2006 page 416 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.5.6 Operation Timing DTC activation request DTC request Data transfer Read Write Vector read Address Transfer information read Transfer information write Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) DTC activation request DTC request Vector read Address Data transfer Read Write Read Write Transfer information read Transfer information write Figure 9.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) Rev. 3.00 Mar 17, 2006 page 417 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) DTC activation request DTC request Vector read Address Read Write Read Write Data transfer Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 9.11 DTC Operation Timing (Example of Chain Transfer) 9.5.7 Number of DTC Execution States Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of states required for each execution status. Table 9.6 DTC Execution Status Vector Read I 1 1 1 Register Information Read/Write J 6 6 6 Data Read K 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer Legend: N: Block size (initial setting of CRAH and CRAL) Rev. 3.00 Mar 17, 2006 page 418 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Table 9.7 Number of States Required for Each Execution Status OnChip RAM 32 1 -- 1 1 1 1 1 1 OnChip ROM 16 1 1 -- 1 1 1 1 1 On-Chip I/O Registers 8 2 -- -- 2 4 2 4 1 16 2 -- -- 2 2 2 2 1 Object to be Accessed Bus width Access states Execution status Vector read SI Register information read/write SJ Byte data read SK Word data read SK Byte data write SL Word data write SL Internal operation SM External Devices 8 2 4 -- 2 4 2 4 1 8 3 16 2 16 3 3+m -- 3+m 3+m 3+m 3+m 1 6+2m 2 -- 3+m -- 2 6+2m 2 3+m 2 6+2m 2 1 1 The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. Rev. 3.00 Mar 17, 2006 page 419 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.6 9.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 9.6.2 Activation by Software The procedure for using the DTC with software activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to SWDTE bit and the vector number to DTVECR. 5. Check the vector number written to DTVECR. 6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 3.00 Mar 17, 2006 page 420 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.7 9.7.1 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. Rev. 3.00 Mar 17, 2006 page 421 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4. Set the start address of the NDR transfer register information to the DTC vector address. 5. Set the bit corresponding to TGIA in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. Rev. 3.00 Mar 17, 2006 page 422 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.7.3 Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.12 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal mode for input data. Set fixed transfer source address (G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, an interrupt request is not sent to the CPU. Rev. 3.00 Mar 17, 2006 page 423 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.12 Chain Transfer when Counter = 0 Rev. 3.00 Mar 17, 2006 page 424 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 3.00 Mar 17, 2006 page 425 of 926 REJ09B0283-0300 Section 9 Data Transfer Controller (DTC) 9.8 9.8.1 Usage Notes Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 22, Power-Down Modes. 9.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. 9.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. * DMAC Transfer End Interrupt When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0. * Chain Transfer When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI and high-speed A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. Rev. 3.00 Mar 17, 2006 page 426 of 926 REJ09B0283-0300 Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports A to E have a built-in pull-up MOS function and a input pull-up MOS control register (PCR) to control the on/off state of input pull-up MOS. Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1 to 3, 5 (P50 to P53), and 6 to 8 can drive a single TTL load and 30 pF capacitive load. Ports A to H can drive a single TTL load and 50 pF capacitive load. All the I/O ports can drive a Darlington transistor when outputting data. Ports 1 and 2 are Schmitt-triggered inputs. Ports 5, 6, F (PF1, PF2), and H (PH2, PH3) are Schmitt-triggered inputs when used as the IRQ input. Rev. 3.00 Mar 17, 2006 page 427 of 926 REJ09B0283-0300 Section 10 I/O Ports Table 10.1 Port Functions Port Description Modes 1 Modes 2 Mode 4 and 5 and 6 Modes 3*1, 7 EXPE = 1 EXPE = 0 Input/ Output Type Port General I/O port P17/PO15/TIOCB2/TCLKD/ 1 also functioning EDRAK3 as PPG outputs, TPU I/Os, and EXDMAC outputs P16/PO14/TIOCA2/EDRAK2 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 Port General I/O port 2 also functioning as PPG outputs, TPU I/Os, interrupt inputs, and EXDMAC outputs P27/PO7/TIOCB5/EDRAK1/ (IRQ15) P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ Schmitttriggered TCLKD/EDRAK3 TCLKD input P16/PO14/TIOCA2/ P16/PO14/TIOCA2 EDRAK2 P27/PO7/TIOCB5/ EDRAK1/(IRQ15) P27/PO7/TIOCB5/ (IRQ15) Schmitttriggered input P26/PO6/TIOCA5/EDRAK0/ (IRQ14) P26/PO6/TIOCA5/ EDRAK0/(IRQ14) P26/PO6/TIOCA5/ (IRQ14) P25/PO5/TIOCB4/(IRQ13) P24/PO4/TIOCA4/(IRQ12) P23/PO3/TIOCD3/(IRQ11) P22/PO2/TIOCC3/(IRQ10) P21/PO1/TIOCB3/(IRQ9) P20/PO0/TIOCA3/(IRQ8) Port General I/O port 3 also functioning as SCI I/Os P35/SCK1/(OE)/CKE*2 P34/SCK0 P33/RxD1 P32/RxD0/IrRxD P31/TxD1 P30/TxD0/IrTxD P35/SCK1/(OE)/ CKE*2 P35/SCK1 Opendrain output capability Rev. 3.00 Mar 17, 2006 page 428 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 1 Modes 2 Mode 4 and 5 and 6 P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port General I/O port 5 also functioning as interrupt inputs, A/D converter analog inputs, and D/A converter analog outputs General I/O port also functioning as interrupt inputs, A/D converter analog inputs, and SCI I/Os Port General I/O port 6 also functioning as interrupt inputs, TMR I/Os, and DMAC I/Os P57/AN15/DA3/IRQ7 P56/AN14/DA2/IRQ6 P55/AN13/IRQ5 P54/AN12/IRQ4 Schmitttriggered input when used as input Modes 3*1, 7 EXPE = 1 EXPE = 0 Input/ Output Type Port Description Port General I/O port 4 also functioning as A/D converter analog inputs and D/A converter analog outputs P53/ADTRG/IRQ3 P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0 P65/TMO1/DACK1/IRQ13 P64/TMO0/DACK0/IRQ12 P63/TMCI1/TEND1/IRQ11 P62/TMCI0/TEND0/IRQ10 P61/TMRI1/DREQ1/IRQ9 P60/TMRI0/DREQ0/IRQ8 Schmitttriggered input when used as input Port General I/O port 7 also functioning as DMAC I/Os and EXDMAC I/Os P75/EDACK1/(DACK1) P74/EDACK0/(DACK0) P73/ETEND1/(TEND1) P72/ETEND0/(TEND0) P71/EDREQ1/(DREQ1) P70/EDREQ0/(DREQ0) P75/EDACK1/ (DACK1) P74/EDACK0/ (DACK0) P73/ETEND1/ (TEND1) P72/ETEND0/ (TEND0) P71/EDREQ1/ (DREQ1) P70/EDREQ0/ (DREQ0) P75/(DACK1) P74/(DACK0) P73/(TEND1) P72/(TEND0) P71/(DREQ1) P70/(DREQ0) Rev. 3.00 Mar 17, 2006 page 429 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 1 Modes 2 Mode 4 and 5 and 6 P85/EDACK3/IRQ5 P84/EDACK2/IRQ4 P83/ETEND3/IRQ3 P82/ETEND2/IRQ2 P81/EDREQ3/IRQ1 P80/EDREQ2/IRQ0 Port General I/O port A also functioning as address outputs PA7/A23 PA6/A22 PA5/A21 A20 A19 A18 A17 A16 Port General I/O port B also functioning as address outputs A15 A14 A13 A12 A11 A10 A9 A8 Port General I/O port C also functioning as address outputs A7 A6 A5 A4 A3 A2 A1 A0 Modes 3*1, 7 EXPE = 1 EXPE = 0 Input/ Output Type Port Description Port General I/O port 8 also functioning as EXDMAC I/Os and interrupt inputs P85/EDACK3/IRQ5 P85/IRQ5 P84/EDACK2/IRQ4 P84/IRQ4 P83/ETEND3/IRQ3 P83/IRQ3 P82/ETEND2/IRQ2 P82/IRQ2 P81/EDREQ3/IRQ1 P81/IRQ1 P80/EDREQ2/IRQ0 P80/IRQ0 PA7/A23 PA7/A23 PA6/A22 PA6/A22 PA5/A21 PA5/A21 PA4/A20 PA4/A20 PA3/A19 PA3/A19 PA2/A18 PA2/A18 PA1/A17 PA1/A17 PA0/A16 PA0/A16 PB7/A15 PB7/A15 PB6/A14 PB6/A14 PB5/A13 PB5/A13 PB4/A12 PB4/A12 PB3/A11 PB3/A11 PB2/A10 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Built-in input pullup MOS Built-in input pullup MOS Built-in input pullup MOS Opendrain output capability Rev. 3.00 Mar 17, 2006 page 430 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 1 Modes 2 Mode 4 and 5 and 6 D15 D14 D13 D12 D11 D10 D9 D8 Port General I/O port E also functioning as data I/Os D7 D6 D5 D4 D3 D2 D1 D0 Port General I/O port F also functioning as interrupt inputs and bus control I/Os PF7/ PF6/AS RD HWR PF3/LWR PF2/LCAS/DQML*2/IRQ15 PF1/UCAS/DQMU*2/IRQ14 PF0/WAIT Port General I/O port G also functioning as bus control I/Os PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3/RAS3/CAS*2 PG2/CS2/RAS2/RAS*2 PG1/CS1 PG0/CS0 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 D15 D14 D13 D12 D11 D10 D9 D8 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PF7/ PF6/AS RD HWR PF3/LWR PF2/LCAS/ DQML*2/IRQ15 PF1/UCAS/ DQMU*2/IRQ14 PF0/WAIT PG6/BREQ PG5/BACK PG4/BREQO PG3/CS3/RAS3/ CAS*2 PG2/CS2/RAS2/ RAS*2 PG1/CS1 PG0/CS0 Modes 3*1, 7 EXPE = 1 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7/ PF6 PF5 PF4 PF3 PF2/IRQ15 Only PF1 and PF2 are Schmitttriggered inputs when used as the IRQ input Built-in input pullup MOS EXPE = 0 Input/ Output Type Built-in input pullup MOS Port Description Port General I/O port D also functioning as data I/Os PF1/IRQ14 PF0 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Rev. 3.00 Mar 17, 2006 page 431 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 1 Modes 2 Mode 4 and 5 and 6 2 Modes 3*1, 7 EXPE = 1 PH3/CS7/OE/ CKE*2/(IRQ7) PH2/CS6/(IRQ6) PH1/CS5/RAS5/ SDRAM*2 PH0/CS4/RAS4/ WE*2 EXPE = 0 PH3/(IRQ7) PH2/(IRQ6) PH1/SDRAM*2 Port Description Input/ Output Type Only PH2 and PH3 are Schmitttriggered inputs when used as the IRQ input Port General I/O port PH3/CS7/OE/CKE* /(IRQ7) H also functioning as interrupt inputs PH2/CS6/(IRQ6) and bus control PH1/CS5/RAS5/SDRAM*2 I/Os PH0/CS4/RAS4/WE*2 PH0 Notes: 1. Mode 3 is not supported in H8S/2678 Group. 2. These pins are not supported in H8S/2678 Group. 10.1 Port 1 Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 register (PORT1) 10.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Rev. 3.00 Mar 17, 2006 page 432 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. PORT1 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P17 P16 P15 P14 P13 P12 P11 P10 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P17 to P10. Rev. 3.00 Mar 17, 2006 page 433 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.1.4 Pin Functions Port 1 pins also function as PPG outputs, TPU I/Os, and EXDMAC outputs. The correspondence between the register specification and the pin functions is shown below. * P17/PO15/TIOCB2/TCLKD/EDRAK3 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, bit EDRAKE in EDMDR3, and bit P17DDR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 3 EDRAKE TPU channel 2 settings P17DDR NDER15 Pin function (1) in table below -- -- TIOCB2 output 0 -- P17 input 0 (2) in table below 1 0 P17 output 1 1 PO15 output 1 1 -- -- -- EDRAK3 output TIOCB2 input* 2 TCLKD input* Modes 3* (EXPE = 0), 7 (EXPE = 0) 3 EDRAKE TPU channel 2 settings P17DDR NDER15 Pin function (1) in table below -- -- TIOCB2 output 0 -- P17 input -- (2) in table below 1 0 P17 output 1 1 1 PO15 output TIOCB2 input* 2 TCLKD input* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. 3. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 434 of 926 REJ09B0283-0300 Section 10 I/O Ports TPU channel 2 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR1, CCLR0 -- Other than B'10 PWM mode 2 output B'10 Output function -- Output compare output -- -- -- x: Don't care * P16/PO14/TIOCA2/EDRAK2 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, bit EDRAKE in EDMDR2 and bit P16DDR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 3 EDRAKE TPU channel 2 settings P16DDR NDER14 Pin function (1) in table below -- -- TIOCA2 output 0 -- P16 input 0 (2) in table below 1 0 P16 output TIOCA input* 1 1 -- 1 1 PO14 output -- -- EDRAK2 output Rev. 3.00 Mar 17, 2006 page 435 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 3 EDRAKE TPU channel 2 settings P16DDR NDER14 Pin function Note: (1) in table below -- -- TIOCA2 output 0 -- P16 input -- (2) in table below 1 0 P16 output 1 TIOCA2 input* 1 1 PO14 output 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. (2) (1) B'0000, B'01xx (2) B'001x (1) B'0010 (1) (2) B'0011 TPU channel 2 settings MD3 to MD0 IOA3 to IOA0 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- Other than B'xx00 CCLR1, CCLR0 -- Other than B'10 B'10 Output function -- Output compare output -- 2 PWM* PWM mode 1 mode 2 output output -- x: Don't care Notes: 2. TIOCB2 output disabled. 3. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 436 of 926 REJ09B0283-0300 Section 10 I/O Ports * P15/PO13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR. TPU channel 1 settings P15DDR NDER13 Pin function (1) in table below -- -- TIOCB1 output 0 -- P15 input (2) in table below 1 0 P15 output 1 1 1 PO13 output TIOCB1 input* 2 TCLKC input* Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01XX and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is TPSC2 to TPSC0 = B'110, or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when phase counting mode is set for channels 2 and 4. TPU channel 1 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR1, CCLR0 -- Other than B'10 PWM mode 2 output B'10 Output function -- Output compare output -- -- -- x: Don't care Rev. 3.00 Mar 17, 2006 page 437 of 926 REJ09B0283-0300 Section 10 I/O Ports * P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR. TPU channel 1 settings P14DDR NDER12 Pin function (1) in table below -- -- TIOCA1 output 0 -- P14 input (2) in table below 1 0 P14 output 1 TIOCA1 input* 1 1 PO12 output Note: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. TPU channel 1 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) B'001x (1) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR1, CCLR0 Other than B'01 B'01 Output function -- Output compare output -- 2 PWM PWM* mode 1 mode 2 output output -- x: Don't care Note: 2. TIOCB1 output disabled. Rev. 3.00 Mar 17, 2006 page 438 of 926 REJ09B0283-0300 Section 10 I/O Ports * P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR. TPU channel 0 settings P13DDR NDER11 Pin function (1) in table below -- -- TIOCD0 output 0 -- P13 input (2) in table below 1 0 P13 output 1 1 1 PO11 output TIOCD0 input* 2 TCLKB input* Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 or B'01xx and IOD3 to IOD0 = B'10xx. 2. TCLKB input when the setting for any of TCR0 to TCR2 is TPSC2 to TPSC0 = B'101. TCLKB input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings MD3 to MD0 IOD3 to IOD0 (2) (1) B'0000 B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2, CCLR0 -- -- Other than B'110 PWM mode 2 output B'110 Output function -- Output compare output -- -- -- x: Don't care Rev. 3.00 Mar 17, 2006 page 439 of 926 REJ09B0283-0300 Section 10 I/O Ports * P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR. TPU channel 0 settings P12DDR NDER10 Pin function (1) in table below -- -- TIOCC0 output 0 -- P12 input (2) in table below 1 0 P12 output 1 1 1 PO10 output TIOCC0 input* 2 TCLKA input* Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for any of TCR0 to TCR5 is TPSC2 to TPSC0 = B'100. TCLKA input when phase counting mode is set for channels 1 and 5. TPU channel 0 settings MD3 to MD0 IOC3 to IOC0 (2) (1) B'0000 (2) B'001x (1) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR2, CCLR0 Other than B'101 B'101 Output function -- Output compare output -- 3 PWM* PWM mode 1 mode 2 output output -- x: Don't care Note: 3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR0. Rev. 3.00 Mar 17, 2006 page 440 of 926 REJ09B0283-0300 Section 10 I/O Ports * P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0 and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit P11DDR. TPU channel 0 settings P11DDR NDER9 Pin function Note: * (1) in table below -- -- TIOCB0 output 0 -- P11 input (2) in table below 1 0 P11 output TIOCB0 input* TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. (2) (1) B'0000 B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) 1 1 PO9 output TPU channel 0 settings MD3 to MD0 IOB3 to IOB0 CCLR2, CCLR0 -- -- Other than B'010 PWM mode 2 output B'010 Output function -- Output compare output -- -- -- x: Don't care Rev. 3.00 Mar 17, 2006 page 441 of 926 REJ09B0283-0300 Section 10 I/O Ports * P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, and bit P10DDR. TPU channel 0 settings P10DDR NDER8 Pin function Note: (1) in table below -- -- TIOCA0 output 0 -- P10 input (2) in table below 1 0 P10 output 1 TIOCA0 input* 1 1 PO8 output 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. (2) (1) B'0000 (2) B'001x (1) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 TPU channel 0 settings MD3 to MD0 IOA3 to IOA0 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR2, CCLR0 Other than B'001 B'001 Output function -- Output compare output -- 2 PWM PWM* mode 1 mode 2 output output -- x: Don't care Note: 2. TIOCB0 output disabled. Rev. 3.00 Mar 17, 2006 page 442 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 register (PORT2) 10.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Rev. 3.00 Mar 17, 2006 page 443 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P27 P26 P25 P24 P23 P22 P21 P20 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P27 to P20. Rev. 3.00 Mar 17, 2006 page 444 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.2.4 Pin Functions Port 2 pins also function as PPG outputs, TPU I/Os, interrupt inputs, and EXDMAC outputs. The correspondence between the register specification and the pin functions is shown below. * P27/PO7/TIOCB5/(IRQ15)/EDRAK1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER7 in NDERL, bit EDRAKE in EDMDR1, bit P27DDR, and bit ITS15 in ITSR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 3 EDRAKE TPU channel 5 settings P27DDR NDER7 Pin function (1) in table below -- -- TIOCB5 output 0 -- P27 input 0 (2) in table below 1 0 P27 output 1 1 PO7 output 1 1 -- -- -- EDRAK1 output TIOCB5 input* 2 IRQ15 interrupt input* Mode 3* (EXPE = 0), 7 (EXPE = 0) 3 EDRAKE TPU channel 5 settings P27DDR NDER7 Pin function (1) in table below -- -- TIOCB5 output 0 -- P27 input -- (2) in table below 1 0 P27 output 1 TIOCB5 input* 2 1 1 PO7 output IRQ15 interrupt input* Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. IRQ15 input when ITS15 = 1. 3. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 445 of 926 REJ09B0283-0300 Section 10 I/O Ports TPU channel 5 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx (2) B'0010 (2) (1) B'0011 Other than B'xx00 (2) B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR1, CCLR0 -- Other than B'10 PWM mode 2 output B'10 Output function -- Output compare output -- -- -- x: Don't care * P26/PO6/TIOCA5/IRQ14/EDRAK0 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER6 in NDERL, bit EDRAKE in EDMDR0, bit P26DDR, and bit ITS14 in ITSR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 4 EDRAKE TPU channel 5 settings P26DDR NDER6 Pin function (1) in table below -- -- TIOCA5 output 0 -- P26 input 0 (2) in table below 1 0 P26 output 1 1 1 -- -- -- EDRAK0 output PO6 output 1 TIOCA input* 2 IRQ14 interrupt input* Rev. 3.00 Mar 17, 2006 page 446 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 4 EDRAKE TPU channel 5 settings P26DDR NDER6 Pin function (1) in table below -- -- TIOCA5 output 0 -- P26 input -- (2) in table below 1 0 P26 output 1 TIOCA5 input* 2 1 1 PO6 output IRQ14 interrupt input* Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. IRQ14 input when ITS14 = 1. TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) B'001x (2) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR1, CCLR0 Other than B'01 B'01 Output function -- Output compare output -- 3 PWM PWM* mode 1 mode 2 output output -- x: Don't care Note: 3. TIOCB5 output disabled. 4. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 447 of 926 REJ09B0283-0300 Section 10 I/O Ports * P25/PO5/TIOCB4/IRQ13 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR. TPU channel 4 settings P25DDR NDER5 Pin function (1) in table below -- -- TIOCB4 output 0 -- P25 input (2) in table below 1 0 P25 output 1 TIOCB4 input* 2 1 1 PO5 output IRQ13 interrupt input* Notes: 1. TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. 2. IRQ13 input when ITS13 = 1. TPU channel 5 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR1, CCLR0 -- -- Other than B'10 PWM mode 2 output B'10 Output function -- Output compare output -- -- -- x: Don't care Rev. 3.00 Mar 17, 2006 page 448 of 926 REJ09B0283-0300 Section 10 I/O Ports * P24/PO4/TIOCA4/IRQ12 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR4 and bits IOA3 to IOA0 in TIOR4), bit NDER4 in NDERL, bit P24DDR, and bit ITS12 in ITSR. TPU channel 4 settings P24DDR NDER4 Pin function (1) in table below -- -- TIOCA4 output 0 -- P24 input (2) in table below 1 0 P24 output 1 TIOCA4 input* 2 1 1 PO4 output IRQ12 interrupt input* Notes: 1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. IRQ12 input when ITS12 = 1. TPU channel 4 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) B'001x (1) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR1, CCLR0 Other than B'01 B'01 Output function -- Output compare output -- 3 PWM* PWM mode 1 mode 2 output output -- x: Don't care Note: 3. TIOCB4 output disabled. Rev. 3.00 Mar 17, 2006 page 449 of 926 REJ09B0283-0300 Section 10 I/O Ports * P23/PO3/TIOCD3/IRQ11 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER3 in NDERL, bit P23DDR, and bit ITS11 in ITSR. TPU channel 3 settings P23DDR NDER3 Pin function (1) in table below -- -- TIOCD3 output 0 -- P23 input (2) in table below 1 0 P23 output 1 TIOCD3 input* 2 1 1 PO3 output IRQ11 interrupt input* Notes: 1. TIOCD3 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 2. IRQ11 input when ITS11 = 1. TPU channel 3 settings MD3 to MD0 IOD3 to IOD0 (2) (1) B'0000 B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- Other than B'110 PWM mode 2 output B'110 -- Output compare output -- -- -- x: Don't care Rev. 3.00 Mar 17, 2006 page 450 of 926 REJ09B0283-0300 Section 10 I/O Ports * P22/PO2/TIOCC3/IRQ10 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR. TPU channel 3 settings P22DDR NDER2 Pin function (1) in table below -- -- TIOCC3 output 0 -- P22 input (2) in table below 1 0 P22 output 1 TIOCC3 input* 2 1 1 PO2 output IRQ10 interrupt input* Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. IRQ10 input when ITS10 = 1. TPU channel 3 settings MD3 to MD0 IOC3 to IOC0 (2) (1) B'0000 (2) B'001x (1) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR2 to CCLR0 Output function Other than B'101 B'101 -- Output compare output -- 3 PWM* PWM mode 1 mode 2 output output -- x: Don't care Note: 3. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR3. Rev. 3.00 Mar 17, 2006 page 451 of 926 REJ09B0283-0300 Section 10 I/O Ports * P21/PO1/TIOCB3/IRQ9 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR. TPU channel 3 settings P21DDR NDER1 Pin function (1) in table below -- -- TIOCB3 output 0 -- P21 input (2) in table below 1 0 P21 output 1 TIOCB3 input* 2 1 1 PO1 output IRQ9 interrupt input* Notes: 1. TIOCB3 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx. 2. IRQ9 input when ITS9 = 1. TPU channel 3 settings MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000 B'0000 B'0001 to B'0011 B'0100 B'0101 to B'0111 B'1xxx -- -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- Other than B'010 PWM mode 2 output B'010 -- Output compare output -- -- -- x: Don't care Rev. 3.00 Mar 17, 2006 page 452 of 926 REJ09B0283-0300 Section 10 I/O Ports * P20/PO0/TIOCA3/IRQ8 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR. TPU channel 3 settings P20DDR NDER0 Pin function (1) in table below -- -- TIOCA3 output 0 -- P20 input (2) in table below 1 0 P20 output 1 TIOCA3 input* 2 1 1 PO0 output IRQ8 interrupt input* Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. IRQ8 input when ITS8 = 1. TPU channel 3 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000 (2) B'001x (1) B'0010 Other than B'xx00 -- (1) (2) B'0011 Other than B'xx00 B'0000 B'0001 to B'0011 B'xx00 B'0100 B'0101 to B'0111 B'1xxx -- -- -- CCLR2 to CCLR0 Output function Other than B'001 B'001 -- Output compare output -- 3 PWM* PWM mode 1 mode 2 output output -- x: Don't care Note: 3. TIOCB3 output disabled. Rev. 3.00 Mar 17, 2006 page 453 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 register (PORT3) * Port 3 open drain control register (P3ODR) * Port function control register 2(PFCR2) 10.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR 0 0 0 0 0 0 W W W W W W When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Rev. 3.00 Mar 17, 2006 page 454 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P35DR P34DR P33DR P32DR P31DR P30DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.3.3 Port 3 Register (PORT3) PORT3 shows the pin states. PORT3 cannot be modified. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 Note: P35 P34 P33 P32 P31 P30 * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R R R R R R If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 1 read is performed while P3DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P35 to P30. Rev. 3.00 Mar 17, 2006 page 455 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. Rev. 3.00 Mar 17, 2006 page 456 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.3.5 Port Function Control Register 2 (PFCR2) P3ODR controls the I/O port. Bit 7 to 4 3 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. ASOE 1 R/W AS Output Enable Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin 2 LWROE 1 R/W LWR Output Enable Selects to enable or disable the LWR output pin. 0: PF3 is designated as I/O port 1: PF3 is designated as LWR output pin 1 OES 1 R/W OE Output Select Selects the OE output pin port when the OEE bit is set to 1 in DRAMCR (enabling OE/CKE* output). 0: P35 is designated as OE output pin 1: PH3 is designated as OE/CKE* output pin 0 DMACS 0 R/W DMAC Control Pin Select Selects the DMAC control I/O port. 0: PF65 to PF60 are designated as DMAC control pins 1: PF75 to PF70 are designated as DMAC control pins Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 457 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.3.6 Pin Functions Port 3 pins also function as SCI I/Os and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. * P35/SCK1/OE/CKE The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits RMTS2 to RMTS0 in DRAMCR, bit OES in PFCR2, and bit P35DDR. Modes 1, 2, 3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1), H8S/2678R Group OEE OES Area 2 to 5 0 -- -- 1 -- Normal space or DRAM space 1 1 1 1 P35 output* -- SCK1 output* -- -- SCK1 output* -- -- -- SCK1 input -- -- -- -- OE output 1 0 Continuous synchronous DRAM space -- -- -- -- CKE output CKE1 C/A CKE0 P35DDR Pin function 0 P35 input 0 1 P35 output* 0 0 1 1 -- SCK1 output* -- -- SCK1 output* 1 -- -- -- SCK1 input 0 P35 input 0 0 0 Modes 1, 2, 4, 5, 6, 7 (EXPE = 1), H8S/2678 Group OEE OES CKE1 C/A CKE0 P35DDR Pin function 0 P35 input 0 1 P35 output* 0 1 -- SCK1 output* 0 1 -- -- SCK1 output* 0 -- 1 -- -- -- SCK1 input 0 P35 input 0 1 P35 output* 0 1 -- SCK1 output* 0 1 -- -- SCK1 output* 1 1 -- -- -- SCK1 input 1 0 -- -- -- -- OE output Note: * NMOS open-drain output when P35ODR = 1. Rev. 3.00 Mar 17, 2006 page 458 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 OEE OES CKE1 C/A CKE0 P35DDR Pin function 0 P35 input 0 1 P35 1 output* 0 0 -- -- -- 1 1 -- SCK1 1 output* -- -- SCK1 1 output* -- -- -- SCK1 input Notes: 1. NMOS open-drain output when P35ODR = 1. 2. Only in H8S/2678R Group. * P34/SCK0 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_0, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 C/A CKE0 P34DDR Pin function Note: * 0 P34 input 0 1 P34 output* 0 1 -- SCK0 output* 0 1 -- -- SCK0 output* 1 -- -- -- SCK0 input NMOS open-drain output when P34ODR = 1. * P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_1 and bit P33DDR. RE P33DDR Pin function Note: * 0 P33 input 0 1 P33 output* 1 -- RxD1 input NMOS open-drain output when P33ODR = 1. Rev. 3.00 Mar 17, 2006 page 459 of 926 REJ09B0283-0300 Section 10 I/O Ports * P32/RxD0/IrRxD The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_0 and bit P32DDR. RE P32DDR Pin function Note: * 0 P32 input 0 1 P32 output* 1 -- RxD0/IrRxD input NMOS open-drain output when P32ODR = 1. * P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P31DDR. TE P31DDR Pin function Note: * 0 P31 input 0 1 P31 output* 1 -- TxD1 output* NMOS open-drain output when P31ODR = 1. * P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR. TE P30DDR Pin function Note: * 0 P30 input 0 1 P30 output* 1 -- RxD0/IrRxD output* NMOS open-drain output when P30ODR = 1. Rev. 3.00 Mar 17, 2006 page 460 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.4 Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. * Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P47 P46 P45 P44 P43 P42 P41 P40 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description The pin states are always read when a port 4 read is performed. Determined by the states of pins P47 to P40. 10.4.2 Pin Functions Port 4 also functions as the A/D converter analog input and D/A converter analog output. The correspondence between pins are as follows. * P47/AN7/DA1 Pin function AN7 input DA1 output * P46/AN6/DA0 Pin function AN6 input DA0 output Rev. 3.00 Mar 17, 2006 page 461 of 926 REJ09B0283-0300 Section 10 I/O Ports * P45/AN5 Pin function AN5 input * P44/AN4 Pin function AN4 input * P43/AN3 Pin function AN3 input * P42/AN2 Pin function AN2 input * P41/AN1 Pin function AN1 input * P40/AN0 Pin function AN0 input 10.5 Port 5 Port 5 comprises a 4-bit I/O port (P53 to P50) and a 4-bit input-only port (P57 to P54). The 4-bit input-only port does not have the data direction register and data register. The port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) * Port 5 register (PORT5) Rev. 3.00 Mar 17, 2006 page 462 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read. Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. P53DDR P52DDR P51DDR P50DDR 0 0 0 0 W W W W When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 10.5.2 Port 5 Data Register (P5DR) P5DR stores output data for the port 5 pins. Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. P53DR P52DR P51DR P50DR 0 0 0 0 R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. Rev. 3.00 Mar 17, 2006 page 463 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name P57 P56 P55 P54 P53 P52 P51 P50 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R If bits P53 to P50 are read while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. Description When bits P57 to P54 are read, the pin states are always read from bits 7 to 4. Determined by the states of pins P57 to P50. 10.5.4 Pin Functions Port 5 pins also function as SCI I/Os, A/D converter inputs, A/D converter analog inputs, D/A converter analog outputs, and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. * P57/AN15/DA3/IRQ7 The pin function is switched as shown below according to bit ITS7 in ITSR. Pin function IRQ7 interrupt input pin* AN15 input DA3 output Note: * IRQ7 input when ITS7 = 0. Rev. 3.00 Mar 17, 2006 page 464 of 926 REJ09B0283-0300 Section 10 I/O Ports * P56/AN14/DA2/IRQ6 The pin function is switched as shown below according to bit ITS6 in ITSR. Pin function IRQ6 interrupt input pin* AN14 input DA2 output Note: * IRQ6 input when ITS6 = 0. * P55/AN13/IRQ5 The pin function is switched as shown below according to bit ITS5 in ITSR. Pin function Note: * IRQ5 input when ITS5 = 0. IRQ5 interrupt input* AN13 input * P54/AN12/IRQ4 The pin function is switched as shown below according to bit ITS4 in ITSR. Pin function Note: * IRQ4 input when ITS4 = 0. IRQ4 interrupt input* AN12 input * P53/ADTRG/IRQ3 The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D control register (ADCR), bit ITS3 in ITSR, and bit P53DDR. P53DDR Pin function 0 P53 input ADTRG input* Notes: 1. ADTRG input when TRGS1 = TRGS0 = 0. 2. IRQ3 input when ITS3 = 0. 1 2 1 P53 output IRQ3 interrupt input* Rev. 3.00 Mar 17, 2006 page 465 of 926 REJ09B0283-0300 Section 10 I/O Ports * P52/SCK2/IRQ2 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 C/A CKE0 P52DDR Pin function 0 P52 input 0 1 P52 output 0 1 -- SCK2 output 0 1 -- -- 1 -- -- -- SCK2 input SCK2 output IRQ2 interrupt input* Note: * IRQ2 input when ITS2 = 0. * P51/RxD2/IRQ1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_2, bit ITS1 in ITSR, and bit P51DDR. RE P51DDR Pin function Note: * 0 P51 input 0 1 P51 output IRQ1 interrupt input* IRQ1 input when ITS1 = 0. 1 -- RxD2 input * P50/TxD2/IRQ0 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_2, bit ITS0 in ITSR, and bit P50DDR. TE P50DDR Pin function Note: * 0 P50 input 0 1 P50 output IRQ0 interrupt input* IRQ0 input when ITS0 = 0. 1 -- TxD2 input Rev. 3.00 Mar 17, 2006 page 466 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.6 Port 6 Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). * Port 6 data direction register (P6DDR) * Port 6 data register (P6DR) * Port 6 register (PORT6) * Port function control register 2 (PFCR2) 10.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR 0 0 0 0 0 0 W W W W W W When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Rev. 3.00 Mar 17, 2006 page 467 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P65DR P64DR P63DR P62DR P61DR P60DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W An output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.6.3 Port 6 Register (PORT6) PORT6 shows the pin states. PORT6 cannot be modified. Bit 7, 6 Bit Name -- Initial Value Undefined R/W -- Description Reserved These bits are reserved, if read they will return an undefined value. 5 4 3 2 1 0 Note: P65 P64 P63 P62 P61 P60 * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R R R R R R If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P65 to P60. Rev. 3.00 Mar 17, 2006 page 468 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.6.4 Pin Functions Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The correspondence between the register specification and the pin functions is shown below. * P65/TMO1/DACK1/IRQ13 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE1 in DMABCRH, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P65DDR, and bit ITS13 in ITSR. SAE1 DMACS OS3 to OS0 P65DDR Pin function 0 P65 input All 0 1 P65 output 0 -- Not all 0 -- TMO1 output 0 P65 input All 0 1 P65 output 1 Not all 0 -- 1 0 -- -- TMO1 DACK1 output output IRQ13 interrupt input* Note: * IRQ13 interrupt input when ITS13 = 0. * P64/TMO0/DACK0/IRQ12 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE0 in DMABCRH, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit P64DDR, and bit ITS12 in ITSR. SAE0 DMACS OS3 to OS0 P64DDR Pin function 0 P64 input All 0 1 P64 output 0 -- Not all 0 -- TMO0 output 0 P64 input All 0 1 1 Not all 0 -- 1 0 -- -- P64 output IRQ12 interrupt input* TMO0 DACK0 output output Note: * IRQ12 interrupt input when ITS12 = 0. Rev. 3.00 Mar 17, 2006 page 469 of 926 REJ09B0283-0300 Section 10 I/O Ports * P63/TMCI1/TEND1/IRQ11 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit TEE1 in DMATCR of the DMAC, bit P63DDR, and bit ITS11 in ITSR. TEE1 DMACS P63DDR Pin function 0 P63 input 0 -- 1 P63 output 0 P63 input 1 1 1 0 -- TEND1 output P63 output 1 IRQ11 interrupt input* TMCI1 input* 2 Notes: 1. IRQ11 interrupt input when ITS11 = 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_1. * P62/TMCI0/TEND0/IRQ10 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit TEE0 in DMATCR of the DMAC, bit P62DDR, and bit ITS10 in ITSR. TEE0 DMACS P62DDR Pin function 0 P62 input 0 -- 1 P62 output 0 P62 input 1 1 1 0 -- TEND0 output P62 output 1 IRQ10 interrupt input* TMCI0 input* 2 Notes: 1. IRQ10 interrupt input when ITS10 = 0. 2. When used as the external clock input pin for the TMR, its pin function should be specified to the external clock input by the CKS2 to CKS0 bits in TCR_0. Rev. 3.00 Mar 17, 2006 page 470 of 926 REJ09B0283-0300 Section 10 I/O Ports * P61/TMRI1/DREQ1/IRQ9 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit P61DDR, and bit ITS9 in ITSR. P61DDR Pin function 0 P61 input TMRI1 input* 2 DREQ1 input* 1 1 P61 output IRQ9 interrupt input* 3 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_1 should be set to 1. 2. DREQ1 input when DMAKS = 0. 3. IRQ9 interrupt input when ITS9 = 0. * P60/TMRI0/DREQ0/IRQ8 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit P60DDR, and bit ITS8 in ITSR. P60DDR Pin function 0 P60 input 1 TMRI0 input* 2 DREQ0 input* 1 P60 output IRQ8 interrupt input* 3 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_0 should be set to 1. 2. DREQ0 input when DMAKS = 0. 3. IRQ8 interrupt input when ITS8 = 0. Rev. 3.00 Mar 17, 2006 page 471 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.7 Port 7 Port 7 is a 6-bit I/O port that also has other functions. The port 7 has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). * Port 7 data direction register (P7DDR) * Port 7 data register (P7DR) * Port 7 register (PORT7) * Port function control register 2 (PFCR2) 10.7.1 Port 7 Data Direction Register (P7DDR) The individual bits of P7DDR specify input or output for the pins of port 7. P7DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR 0 0 0 0 0 0 W W W W W W When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Rev. 3.00 Mar 17, 2006 page 472 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.7.2 Port 7 Data Register (P7DR) P7DR stores output data for the port 7 pins. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P75DR P74DR P73DR P72DR P71DR P70DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.7.3 Port 7 Register (PORT7) PORT7 shows the pin states. PORT7 cannot be modified. Bit 7, 6 Bit Name -- Initial Value Undefined R/W -- Description Reserved These bits are reserved, if read they will return an undefined value. 5 4 3 2 1 0 Note: P75 P74 P73 P72 P71 P70 * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R R R R R R If a port 7 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 7 read is performed while P7DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P75 to P70. Rev. 3.00 Mar 17, 2006 page 473 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.7.4 Pin Functions Port 7 pins also function as DMAC I/Os and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. * P75/DACK1/EDACK1 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE1 in DMABCRH, bit AMS in EDMDR_1, and bit P75DDR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) AMS SAE1 DMACS P75DDR Pin function 0 P75 input 0 -- 1 P75 output 0 P75 input 0 1 P75 output 0 1 1 -- 1 -- -- -- DACK1 EDACK1 output output Modes 3* (EXPE = 0), 7 (EXPE = 0) AMS SAE1 DMACS P75DDR Pin function Note: * 0 P75 input 0 -- 1 P75 output 0 P75 input 0 1 P75 output -- 1 1 -- DACK1 output Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 474 of 926 REJ09B0283-0300 Section 10 I/O Ports * P74/DACK0/EDACK0 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit SAE0 in DMABCRH, bit AMS in EDMDR_0, and bit P74DDR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) AMS SAE0 DMACS P74DDR Pin function 0 P74 input 0 -- 1 P74 output 0 P74 input 0 1 P74 output 0 1 1 -- 1 -- -- -- DACK0 EDACK0 output output Modes 3* (EXPE = 0), 7 (EXPE = 0) AMS SAE0 DMACS P74DDR Pin function Note: * 0 P74 input 0 -- 1 P74 output 0 P74 input 0 1 P74 output -- 1 1 -- DACK0 output Only in H8S/2678R Group. * P73/TEND1/ETEND1 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit TEE1 in DMATCR of the DMAC, bit ETENDE in EDMDR_1 of the EXDMAC, and bit P73DDR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) ETENDE TEE1 DMACS P73DDR Pin function 0 P73 input 0 -- 1 P73 output 0 P73 input 0 1 P73 output 0 1 1 -- TEND1 output 1 -- -- -- ETEND1 output Rev. 3.00 Mar 17, 2006 page 475 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) ETENDE TEE1 DMACS P73DDR Pin function Note: * 0 P73 input 0 -- 1 P73 output 0 P73 input 0 1 P73 output -- 1 1 -- TEND1 output Only in H8S/2678R Group. * P72/TEND0/ETEND0 The pin function is switched as shown below according to the combination of bit DMACS in PFCR2, bit TEE0 in DMATCR of the DMAC, bit ETENDE in EDMDR_0 of the EXDMAC, and bit P72DDR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) ETENDE TEE0 DMACS P72DDR Pin function 0 P72 input 0 -- 1 P72 output 0 P72 input 0 1 P72 output 0 1 1 -- TEND0 output 1 -- -- -- ETEND0 output Modes 3* (EXPE = 0), 7 (EXPE = 0) ETENDE TEE0 DMACS P72DDR Pin function Note: * 0 P72 input 0 -- 1 P72 output 0 P72 input 0 1 P72 output -- 1 1 -- TEND0 output Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 476 of 926 REJ09B0283-0300 Section 10 I/O Ports * P71/DREQ1/EDREQ1 The pin function is switched as shown below according to the combination of bit P71DDR and bit DMACS in PFCR2. P71DDR Pin function 0 P71 input DREQ1 input* EDREQ1 input Note: * DREQ1 input when DMACS = 1. 1 P71 output * P70/DREQ0/EDREQ0 The pin function is switched as shown below according to the combination of bit P70DDR and bit DMACS in PFCR2. P70DDR Pin function 0 P70 input DREQ0 input* EDREQ0 input Note: * DREQ0 input when DMACS = 1. 1 P70 output Rev. 3.00 Mar 17, 2006 page 477 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.8 Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) * Port 8 register (PORT8) 10.8.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR 0 0 0 0 0 0 W W W W W W When a pin function is specified to a general purpose I/O, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Rev. 3.00 Mar 17, 2006 page 478 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.8.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit 7, 6 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. 5 4 3 2 1 0 P85DR P84DR P83DR P82DR P81DR P80DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.8.3 Port 8 Register (PORT8) PORT8 shows the pin states. PORT8 cannot be modified. Bit 7, 6 Bit Name -- Initial Value Undefined R/W -- Description Reserved These bits are reserved, if read they will return an undefined value. 5 4 3 2 1 0 Note: P85 P84 P83 P82 P81 P80 * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R R R R R R If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read. If a port 8 read is performed while P8DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P85 to P80. Rev. 3.00 Mar 17, 2006 page 479 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.8.4 Pin Functions Port 8 pins also function as interrupt inputs and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. * P85/(IRQ5)/EDACK3 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_3 of the EXDMAC, bit P85DDR, and bit ITS5 in ITSR. Modes 1, 2, 3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) AMS P85DDR Pin function 0 P85 input 0 1 P85 output IRQ5 interrupt input* 1 -- EDACK3 output Modes 3, 7 (EXPE = 0) AMS P85DDR Pin function Note: * 0 P85 input -- 1 P85 output IRQ5 interrupt input* IRQ5 input when ITS5 = 1. * P84/(IRQ4)/EDACK2 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 2 AMS P84DDR Pin function 0 P84 input 0 1 P84 input/output IRQ4 interrupt input* 1 1 -- EDACK2 output Rev. 3.00 Mar 17, 2006 page 480 of 926 REJ09B0283-0300 Section 10 I/O Ports Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 AMS P84DDR Pin function 0 P84 input -- 1 P84 output IRQ4 interrupt input* 1 Notes: 1. IRQ4 input when ITS4 = 1. 2. Only in H8S/2678R Group. * P83/(IRQ3)/ETEND3 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of the EXDMAC, bit P83DDR, and bit ITS3 in ITSR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 2 ETENDE P83DDR Pin function 0 P83 input 0 1 P83 output IRQ3 interrupt input* 1 1 -- ETEND3 output Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 ETENDE P83DDR Pin function 0 P83 input -- 1 P83 output 1 IRQ3 interrupt input* Notes: 1. IRQ3 input when ITS3 = 1. 2. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 481 of 926 REJ09B0283-0300 Section 10 I/O Ports * P82/(IRQ2)/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR. Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1) 2 ETENDE P82DDR Pin function 0 P82 input 0 1 P82 output 1 IRQ2 interrupt input* 1 -- ETEND2 output Modes 3* (EXPE = 0), 7 (EXPE = 0) 2 ETENDE P82DDR Pin function 0 P82 input -- 1 P82 output *1 IRQ2 interrupt input Notes: 1. IRQ2 input when ITS2 = 1. 2. Only in H8S/2678R Group. * P81/(IRQ1)/EDREQ3 The pin function is switched as shown below according to the combination of bit P81DDR and bit ITS1 in ITSR. P81DDR Pin function 0 P81 input EDREQ3 input IRQ1 interrupt input* Note: * IRQ1 input when ITS1 = 1. 1 P81 output Rev. 3.00 Mar 17, 2006 page 482 of 926 REJ09B0283-0300 Section 10 I/O Ports * P80/(IRQ0)/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and bit ITS0 in ITSR. P80DDR Pin function 0 P80 input EDREQ2 input IRQ0 interrupt input* Note: * IRQ0 input when ITS0 = 1. 1 P80 output 10.9 Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers. * Port A data direction register (PADDR) * Port A data register (PADR) * Port A register (PORTA) * Port A pull-up MOS control register (PAPCR) * Port A open-drain control register (PAODR) * Port function control register 1 (PFCR1) Rev. 3.00 Mar 17, 2006 page 483 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description * Modes 1, 2, 5, and 6 Pins PA4 to PA0 are address outputs regardless of the PADDR settings. For pins PA7 to PA5, when the corresponding bit of A23E to A21E is set to 1, setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Clearing one of bits A23E to A21E to 0 makes the corresponding port A pin an I/O port, and its function can be switched with PADDR. * Mode 4 When the corresponding bit of A23E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Clearing one of bits A23E to A16E to 0 makes the corresponding port A pin an I/O port, and its function can be switched with PADDR. * Modes 3* and 7 (when EXPE = 1) When the corresponding bit of A23E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Clearing one of bits A23E to A16E to 0 makes the corresponding port A pin an I/O port; setting the corresponding PADDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 3* and 7 (when EXPE = 0) Port A is an I/O port, and its pin functions can be switched with PADDR. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 484 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.9.3 Port A Register (PORTA) PORTA shows port A pin states. PORTA cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. Determined by the states of pins PA7 to PA0. Rev. 3.00 Mar 17, 2006 page 485 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls the input pull-up MOS function. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are valid in modes 3*, 4, and 7. Note: * Only in H8S/2678R Group. Bit 7 6 5 4 3 2 1 0 Bit Name PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin function is specified to an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 10.9.5 Port A Open Drain Control Register (PAODR) PAODR specifies an output type of port A. Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting the corresponding bit to 1 specifies a pin output type to NMOS open-drain output, while clearing this bit to 0 specifies that to CMOS output. 10.9.6 Port Function Control Register 1 (PFCR1) PFCR1 performs I/O port control. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are valid in modes 3*, 4, and 7. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 486 of 926 REJ09B0283-0300 Section 10 I/O Ports Bit 7 Bit Name A23E Initial Value 1 R/W R/W Description Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 6 A22E 1 R/W Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 5 A21E 1 R/W Address 21 Enable Enables or disables output for address output 21 (A21). 0: DR output when PA5DDR = 1 1: A21 output when PA5DDR = 1 4 A20E 1 R/W Address 20 Enable Enables or disables output for address output 20 (A20). 0: DR output when PA4DDR = 1 1: A20 output when PA4DDR = 1 3 A19E 1 R/W Address 19 Enable Enables or disables output for address output 19 (A19). 0: DR output when PA3DDR = 1 1: A19 output when PA3DDR = 1 2 A18E 1 R/W Address 18 Enable Enables or disables output for address output 18 (A18). 0: DR output when PA2DDR = 1 1: A18 output when PA2DDR = 1 1 A17E 1 R/W Address 17 Enable Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1 0 A16E 1 R/W Address 16 Enable Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1 Rev. 3.00 Mar 17, 2006 page 487 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.9.7 Pin Functions Port A pins also function as address outputs. The correspondence between the register specification and the pin functions is shown below. * PA7/A23, PA6/A22, PA5/A21 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A23E to A21E, and bit PADDR. Operating mode EXPE AxxE PADDR Pin function 0 PA input 0 1 PA output 0 PA input 1, 2, 4, 5, 6 -- 1 1 Address output 0 PA input 0 -- 1 PA output 0 PA input 0 1 PA output 0 PA input 3*, 7 1 1 1 Address output Note: * Only in H8S/2678R Group. * PA4/A20, PA3/A19, PA2/A18, PA1/A17, PA20/A16 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A23E to A21E, and bit PADDR. Operating mode EXPE AxxE PADDR Pin function 1, 2, 5, 6 -- -- -- Address output 0 PA input 0 1 PA output 0 PA input 4 -- 1 1 Address output 0 PA input 0 -- 1 PA output 0 PA input 0 1 PA output 0 PA input 3*, 7 1 1 1 Address output Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 488 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.9.8 Port A Input Pull-Up MOS States Port A has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used by pins PA7 to PA5 in modes 1, 2, 5, and 6, and by all pins in modes 3*, 4, and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. Table 10.2 summarizes the input pull-up MOS states. Table 10.2 Input Pull-Up MOS States (Port A) Mode 3*, 4, 7 1, 2, 5, 6 PA7 to PA0 PA7 to PA5 PA4 to PA0 Legend: Off: Input pull-up MOS is always off. On/Off: On when PADDR = 0 and PAPCR = 1; otherwise off. Note: * Only in H8S/2678R Group. Off Reset Hardware Standby Mode Off Software Standby Mode On/Off On/Off Off In Other Operations On/Off On/Off Off 10.10 Port B Port B is an 8-bit I/O port that also has other functions. The port B has the following registers. * Port B data direction register (PBDDR) * Port B data register (PBDR) * Port B register (PORTB) * Port B pull-up MOS control register (PBPCR) Rev. 3.00 Mar 17, 2006 page 489 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description * Modes 1, 2, 5, and 6 Port B pins are address outputs regardless of the PBDDR settings. * Modes 3* (EXPE = 1), 4, and 7 (when EXPE = 1) Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. * Modes 3* (EXPE = 1) and 7 (when EXPE = 0) Port B is an I/O port, and its pin functions can be switched with PBDDR. Note: * Only in H8S/2678R Group. 10.10.2 Port B Data Register (PBDR) PBDR is stores output data for the port B pins. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose I/O. Rev. 3.00 Mar 17, 2006 page 490 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.10.3 Port B Register (PORTB) PORTB shows port B pin states. PORTB cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PB7 to PB0. 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls the on/off state of input pull-up MOS of port B. PBPCR is valid in modes 3, 4, and 7. Bit 7 6 5 4 3 2 1 0 Bit Name PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin function is specified to an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. Rev. 3.00 Mar 17, 2006 page 491 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.10.5 Pin Functions Port B pins also function as address outputs. The correspondence between the register specification and the pin functions is shown below. * PB7/A15, PB6/A14, PB5/A13, PB4/A12, PB3/A11, PB2/A10, PB1/A9, PB0/A8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PBDDR. Operating mode EXPE PBDDR Pin function Note: * 1, 2, 5, 6 -- -- Address output 0 PB input 4 -- 1 Address output 0 PB input 0 1 PB output 0 PB input 3* , 7 1 1 Address output Only in H8S/2678R Group. 10.10.6 Port B Input Pull-Up MOS States Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3, 4, and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.3 summarizes the input pull-up MOS states. Table 10.3 Input Pull-Up MOS States (Port B) Mode 1, 2, 5, 6 3*, 4, 7 Off Reset Hardware Standby Mode Off Software Standby Mode Off On/Off Off On/Off In Other Operations Legend: Off: Input pull-up MOS is always off. On/Off: On when PBDDR = 0 and PBPCR = 1; otherwise off. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 492 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.11 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. * Port C data direction register (PCDDR) * Port C data register (PCDR) * Port C register (PORTC) * Port C pull-up MOS control register (PCPCR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description * Modes 1, 2, 5, and 6 Port C pins are address outputs regardless of the PCDDR settings. * Modes 3* (EXPE = 1), 4, and 7 (when EXPE = 1) Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Modes 3* (EXPE = 1) and 7 (when EXPE = 0) Port C is an I/O port, and its pin functions can be switched with PCDDR. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 493 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.11.3 Port C Register (PORTC) PORTC is shows port C pin states. PORTC cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PC7 to PC0. Rev. 3.00 Mar 17, 2006 page 494 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls the on/off state of input pull-up MOS of port C. PCPCR is valid in modes 3*, 4, and 7. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR * Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin function is specified to an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. Only in H8S/2678R Group. 10.11.5 Pin Functions Port C pins also function as address outputs. The correspondence between the register specification and the pin functions is shown below. * PC7/A7, PC6/A6, PC5/A5, PC4/A4, PC3/A3, PC2/A2, PC1/A1, PC0/A0 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PCDDR. Operating mode EXPE PCDDR Pin function Note: * 1, 2, 5, 6 -- -- Address output 0 PC input 4 -- 1 Address output 0 PC input 0 1 PC output 0 PC input 3* , 7 1 1 Address output Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 495 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.11.6 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3*, 4, and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3*, 4, and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.4 summarizes the input pull-up MOS states. Table 10.4 Input Pull-Up MOS States (Port C) Mode 1, 2, 5, 6 3*, 4, 7 Off Reset Hardware Standby Mode Off Software Standby Mode Off On/Off Off On/Off In Other Operations Legend: Off: Input pull-up MOS is always off. On/Off: On when PCDDR = 0 and PCPCR = 1; otherwise off. Note: * Only in H8S/2678R Group. 10.12 Port D Port D is an 8-bit I/O port that also has other functions. The port D has the following registers. * Port D data direction register (PDDDR) * Port D data register (PDDR) * Port D register (PORTD) * Port D pull-up MOS control register (PDPCR) Rev. 3.00 Mar 17, 2006 page 496 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR * Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description * Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, and 7 (when EXPE = 1) Port D is automatically designated for data input/output. * Modes 3* (EXPE = 1) and 7 (when EXPE = 0) Port D is an I/O port, and its pin functions can be switched with PDDDR. Only in H8S/2678R Group. 10.12.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. Rev. 3.00 Mar 17, 2006 page 497 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.12.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PD7 to PD0. 10.12.4 Port D Pull-up Control Register (PDPCR) PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in modes 3* and 7. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR * Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pin is in its input state, the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 498 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.12.5 Pin Functions Port D pins also function as data I/Os. The correspondence between the register specification and the pin functions is shown below. * PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PDDDR. Operating mode EXPE PDDDR Pin function Note: * 1, 2, 4, 5, 6 -- -- Data I/O Only in H8S/2678R Group. 0 PD input 0 1 PD output 3*, 7 1 -- Data I/O 10.12.6 Port D Input Pull-Up MOS States Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3* and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3* and 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Note: * Only in H8S/2678R Group. Table 10.5 summarizes the input pull-up MOS states. Table 10.5 Input Pull-Up MOS States (Port D) Mode 1, 2, 4, 5, 6 3* , 7 Off Reset Hardware Standby Mode Off Software Standby Mode Off On/Off Off On/Off In Other Operations Legend: OFF: Input pull-up MOS is always off. On/Off: On when PDDDR = 0 and PDPCR = 1; otherwise off. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 499 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.13 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. * Port E data direction register (PEDDR) * Port E data register (PEDR) * Port E register (PORTE) * Port E pull-up MOS control register (PEPCR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description * Modes 1, 2, 4, 5, and 6 When 8-bit bus mode is selected, port E functions as an I/O port. The pin states can be changed with PEDDR. When 16-bit bus mode is selected, port E is designated for data input/output. For details on 8-bit and 16-bit bus modes, see section 6, Bus Controller (BSC). * Modes 3* and 7 (when EXPE = 1) When 8-bit bus mode is selected, port E functions as an I/O port. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, port E is designated for data input/output. * Modes 3* and 7 (when EXPE = 0) Port E is an I/O port, and its pin functions can be switched with PEDDR. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 500 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.13.3 Port E Register (PORTE) PORTE shows port E pin states. PORTE cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PE7 to PE0. Rev. 3.00 Mar 17, 2006 page 501 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.13.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit 7 6 5 4 3 2 1 0 Bit Name PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pin is in its input state, the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 10.13.5 Pin Functions Port E pins also function as data I/Os. The correspondence between the register specification and the pin functions is shown below. * PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0 The pin function is switched as shown below according to the operating mode, bus mode, bit EXPE, and bit PEDDR. Operating mode Bus mode 1, 2, 4, 5, 6 All areas 8-bit space At least one area 16-bit space -- 1 -- 0 PE input -- 3*, 7 All areas 8-bit space At least one area 16-bit space 1 1 -- EXPE PEDDR Pin function Note: * 0 PE input -- 0 1 PE output 0 PE input 1 PE Data I/O output PE Data I/O output Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 502 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.13.6 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode. Input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states. Table 10.6 Input Pull-Up MOS States (Port E) Mode* 1 to 7 8-bit bus 16-bit bus Legend: Off: Input pull-up MOS is always off. On/Off: On when PEDDR = 0 and PEPCR = 1; otherwise off. Note: * Mode 3 is available only in H8S/2678R Group. Off Reset Hardware Standby Mode Off Software Standby Mode On/Off Off In Other Operations On/Off Off 10.14 Port F Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). * Port F data direction register (PFDDR) * Port F data register (PFDR) * Port F register (PORTF) * Port Function Control Register 2 (PFCR2) Rev. 3.00 Mar 17, 2006 page 503 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Initial Value 1/0* 0 0 0 0 0 0 0 1 R/W W W W W W W W W Description * Modes 1, 2, 4, 5, and 6 Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pin PF6 functions as the AS output pin when ASOE is set to 1. When ASOE is cleared to 0, pin PF6 is an I/O port and its function can be switched with PF6DDR. Pins PF5 and PF4 are automatically designated as bus control outputs (RD and HWR). Pin PF3 functions as the LWR output pin when LWROE is set to 1. When LWROE is cleared to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR. Pins PF2 and PF1 are designated as I/O ports and their function can be switched with PFDDR. Pins PF0 functions as bus control input/output pin (LCAS, UCAS, and WAIT) when the appropriate bus controller settings are made. Otherwise, these pins are output ports when the corresponding PFDDR bit is set to 1, and input ports when the bit is cleared to 0. * 2 Modes 3* and 7 (when EXPE = 1) Pin PF7 to PF3 function in the same way as in modes 1, 2, 4, 5, and 6. Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when the appropriate PFCR2 settings are made. Otherwise, these pins are I/O ports, and their functions can be switched with PFDDR. Rev. 3.00 Mar 17, 2006 page 504 of 926 REJ09B0283-0300 Section 10 I/O Ports Bit Bit Name Initial Value R/W Description * 2 Modes 3* and 7 (when EXPE = 0) Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR. Notes: 1. PF7DDR is initialized to 1 in modes 1, 2, 4, 5, and 6, and to 0 in mode 7. 2. Only in H8S/2678R Group. 10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit 7 6 5 4 3 2 1 0 Bit Name PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin function is specified to a general purpose I/O. Rev. 3.00 Mar 17, 2006 page 505 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.14.3 Port F Register (PORTF) PORTF shows port F pin states. PORTF cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PF7 to PF0. 10.14.4 Pin Functions Port F pins also function as external interrupt inputs, bus control signal I/Os, and system clock outputs (). The correspondence between the register specification and the pin functions is shown below. * PF7/ The pin function is switched as shown below according to bit PF7DDR. Operating mode PFDDR Pin function 0 PF7 input 1 to 7 1 output Rev. 3.00 Mar 17, 2006 page 506 of 926 REJ09B0283-0300 Section 10 I/O Ports * PF6/AS The pin function is switched as shown below according to the operating mode, bit EXPE, bit PF6DDR, and bit ASOE. Operating mode EXPE ASOE PF6DDR Pin function Note: * 1 -- AS output 0 PF6 input 1, 2, 4, 5, 6 -- 0 1 PF6 output 0 PF6 input 0 -- 1 PF6 output 1 -- AS output 0 PF6 input 3*, 7 1 0 1 PF6 output Only in H8S/2678R Group. * PF5/RD The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF5DDR. Operating mode EXPE PF5DDR Pin function Note: * 1, 2, 4, 5, 6 -- -- RD output Only in H8S/2678R Group. 0 PF5 input 0 1 PF5 output 3*, 7 1 -- RD output * PF4/HWR The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF4DDR. Operating mode EXPE PF4DDR Pin function Note: * 1, 2, 4, 5, 6 -- -- HWR output Only in H8S/2678R Group. 0 PF4 input 0 1 PF4 output 3*, 7 1 -- HWR output Rev. 3.00 Mar 17, 2006 page 507 of 926 REJ09B0283-0300 Section 10 I/O Ports * PF3/LWR The pin function is switched as shown below according to the operating mode, bit EXPE, bit PF3DDR, and bit LWROE. Operating mode EXPE LWROD PF3DDR Pin function Note: * 1 -- LWR output 0 PF3 input 1, 2, 4, 5, 6 -- 0 1 PF3 output 0 PF3 input 0 -- 1 PF3 output 1 -- LWR output 0 PF3 input 3*, 7 1 0 1 PF3 output Only in H8S/2678R Group. 2 * PF2/LCAS/DQML* /IRQ15 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR. Operating mode EXPE Areas 2 to 5 Any DRAM space area is 16-bit bus space -- LCAS output 1, 2, 4, 5, 6 -- All DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space 0 PF2 input 1 PF2 output 0 PF2 input 0 -- Any DRAM space area is 16-bit bus space 1 PF2 output -- 3* , 7 2 1 All DRAM space areas are 8-bit bus space, or areas 2 to 5 are all normal space 0 PF2 input 1 PF2 output PF2DDR Pin function LCAS output 1 IRQ15 interrupt input* Notes: 1. IRQ15 interrupt input when bit ITS15 is cleared to 0 in ITSR. 2. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 508 of 926 REJ09B0283-0300 Section 10 I/O Ports * PF1/UCAS/DQMU* /IRQ14 2 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR. Operating mode EXPE Areas 2 to 5 1, 2, 4, 5, -- Any of Areas 2 to 5 areas are all normal 2 to 5 space is DRAM space -- UCAS output 0 PF1 input 1 PF1 output 0 PF1 input 0 -- 3* , 7 2 1 Any of Areas 2 to 5 areas are all normal 2 to 5 space is DRAM space 1 -- 0 PF1 input 1 PF1 output PF1DDR Pin function PF1 UCAS output output 1 IRQ14 interrupt* Notes: 1. IRQ14 interrupt input when bit ITS14 is cleared to 0 in ITSR. 2. Only in H8S/2678R Group. * PF0/WAIT The pin function is switched as shown below according to the operating mode, bit EXPE, bit WAITE in BCR, and bit PF0DDR. Operating mode EXPE WAITE PF0DDR Pin function Note: * 0 PF0 input 0 1 PF0 output 1, 2, 4, 5, 6 -- 1 -- WAIT input 0 PF0 input 0 -- 1 PF0 output 0 PF0 input 0 1 PF0 output 3*, 7 1 1 -- WAIT input Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 509 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.15 Port G Port G is a 7-bit I/O port that also has other functions. The port G has the following registers. * Port G data direction register (PGDDR) * Port G data register (PGDR) * Port G register (PORTG) * Port Function Control Register 0 (PFCR0) 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read. Rev. 3.00 Mar 17, 2006 page 510 of 926 REJ09B0283-0300 Section 10 I/O Ports Bit 7 6 5 4 3 2 1 0 Bit Name -- PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Initial Value 0 0 0 0 0 0 0 1/0* 1 R/W -- W W W W W W W Description Reserved If read, it returns an undefined value. * Modes 1, 2, 4, 5, and 6 Pins PG6 to PG4 function as bus control input/output pins (BREQO, BACK, and BREQ) when the appropriate bus controller settings are made. Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR. When the CS output enable bits (CS3E to CS0E) are set to 1, pins PG3 to PG0 function as CS output pins when the corresponding PGDDR bit is set to 1, and as input ports when the bit is cleared to 0. When CS3E to CS0E are cleared to 0, pins PG3 to PG0 are I/O ports, and their functions can be switched with PGDDR. * Modes 3* , 7 (when EXPE = 1) 2 Pins PG6 to PG4 function as bus control input/output pins (BREQO, BACK, and BREQ) when the appropriate bus controller settings are made. Otherwise, these pins are output ports when the corresponding PGDDR bit is set to 1, and as input ports when the bit is cleared to 0. When the CS output enable bits (CS3E to CS0E) are set to 1, pins PG3 to PG0 function as CS output pins when the corresponding PGDDR bit is set to 1, and as input ports when the bit is cleared to 0. When CS3E to CS0E are cleared to 0, pins PG3 to PG0 are I/O ports, and their functions can be switched with PGDDR. * 2 Modes 3* , 7 (when EXPE = 0) Pins PG6 to PG0 are I/O ports, and their functions can be switched with PGDDR. Notes: 1. PG0DDR is initialized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 3, 4, and 7. 2. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 511 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit 7 6 5 4 3 2 1 0 Bit Name -- PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR Initial Value 0 0 0 0 0 0 0 0 R/W -- R/W R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 0, and cannot be modified. An output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.15.3 Port G Register (PORTG) PORTG shows port G pin states. PORTG cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: Bit Name -- PG6 PG5 PG4 PG3 PG2 PG1 PG0 * Initial Value Undefined Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W -- R R R R R R R Description Reserved If this bit is read, it will return an undefined value. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PG6 to PG0. Rev. 3.00 Mar 17, 2006 page 512 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.15.4 Port Function Control Register 0 (PFCR0) PFCR0 performs I/O port control. Bit 7 6 5 4 3 2 1 0 Bit Name CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description CS7 to CS0 Enable These bits enable or disable the corresponding CSn output. 0: Pin is designated as I/O port 1: Pin is designated as CSn output pin (n = 7 to 0) 10.15.5 Pin Functions Port G pins also function as bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below. * PG6/BREQ The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG6DDR. Operating mode EXPE BRLE PG6DDR Pin function Note: * 0 PG6 input 0 1 PG6 output 1, 2, 4, 5, 6 -- 1 -- BREQ input 0 PG6 input 0 -- 1 PG6 output 0 PG6 input 0 1 PG6 output 3*, 7 1 1 -- BREQ input Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 513 of 926 REJ09B0283-0300 Section 10 I/O Ports * PG5/BACK The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG5DDR. Operating mode EXPE BRLE PG5DDR Pin function Note: * 0 PG5 input 0 1 PG5 output 1, 2, 4, 5, 6 -- 1 -- BACK output 0 PG5 input 0 -- 1 PG5 output 0 PG5 input 0 1 PG5 output 3*, 7 1 1 -- BACK output Only in H8S/2678R Group. * PG4/BREQO The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, bit BREQO, and bit PG4DDR. Operating mode EXPE BRLE BREQO PG4DDR Pin function 0 0 -- 1 0 0 1 1, 2, 4, 5, 6 -- 1 1 -- 0 0 -- -- 1 0 0 -- 1 0 0 1 3* , 7 1 1 1 -- PG4 PG4 PG4 PG4 BREQO PG4 PG4 PG4 PG4 PG4 PG4 BREQO input output input output output input output input output input output output Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 514 of 926 REJ09B0283-0300 Section 10 I/O Ports * PG3/CS3/RAS3*/CAS*, PG2/CS2/RAS2*/RAS* The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits RMTS2 to RMTS0. Operating mode EXPE CSnE RMTS2 to RMTS0 0 -- Area n normal space 1, 2, 4, 5, 6 3*, 7 -- 1 Area n DRAM space Area 3 Area 2 synchro- synchronous nous DRAM* DRAM* space space -- CAS* output -- RAS* output 0 0 -- -- 0 -- Area n normal space 1 1 Area n DRAM space Area 3 Area 2 synchro- synchronous nous DRAM* DRAM* space space -- CAS* output -- RAS* output PGnDDR 0 1 0 1 -- RASn output 1 0 1 0 1 -- RASn output Pin function PGn PGn PGn CSn input output input output PGn PGn PGn PGn PGn CSn input output input output input output (n = 3 or 2) Note: * Only in H8S/2678R Group. * PG1/CS1, PG0/CS0 The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, and bit CSnE. Operating mode EXPE CSnE PGnDDR Pin function 0 PGn input 0 1 PGn output 0 PGn input 1, 2, 4, 5, 6 -- 1 1 CSn output 0 PGn input 0 -- 1 PGn output 0 PGn input 0 1 PGn output 0 PGn input 3*, 7 1 1 1 CSn output (n =1 or 0) Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 515 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.16 Port H Port H is a 4-bit I/O port that also has other functions. The port H has the following registers. For details on the port function control register 0, refer to section 10.15.4, Port Function Control Register 0 (PFCR0), and for details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). * Port H data direction register (PHDDR) * Port H data register (PHDR) * Port H register (PORTH) * Port Function Control Register 0 (PFCR0) * Port Function Control Register 2 (PFCR2) Rev. 3.00 Mar 17, 2006 page 516 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.16.1 Port H Data Direction Register (PHDDR) The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 0 R/W -- Description Reserved If these bits are read, they will return an undefined value. PH3DDR PH2DDR PH1DDR PH0DDR 0 0 0 0 W W W W * Modes 1, 2, 3* (when EXPE = 1), 4, 5, 6, and 7 (when EXPE = 1) When the OE output enable bit (OEE) and OE output select bit (OES) are set to 1, pin PH3 functions as the OE output pin. Otherwise, when bit CS7E is set to 1, pin PH3 functions as a CS output pin when the corresponding PHDDR bit is set to 1, and as an input port when the bit is cleared to 0. When bit CS7E is cleared to 0, pin PH3 is an I/O port, and its function can be switched with PHDDR. When the CS output enable bits (CS6E to CS4E) are set to 1, pins PH2 to PH0 function as CS output pins when the corresponding PHDDR bit is set to 1, and as I/O ports when the bit is cleared to 0. When CS6E to CS4E are cleared to 0, pins PH2 to PH0 are I/O ports, and their functions can be switched with PHDDR. * Mode 3* (EXPE = 0) and Mode 7 (when EXPE = 0) Pins PH3 to PH0 are I/O ports, and their functions can be switched with PHDDR. Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 517 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are reserved; they are always read as 0 and cannot be modified. PH3DR PH2DR PH1DR PH0DR 0 0 0 0 R/W R/W R/W R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows port H pin states. PORTH cannot be modified. Bit 7 to 4 3 2 1 0 Note: Bit Name -- Initial Value Undefined R/W -- Description Reserved If these bits are read, they will return an undefined value. PH3 PH2 PH1 PH0 * Undefined* Undefined* Undefined* Undefined* R R R R If a port H read is performed while PHDDR bits are set to 1, the PHDR values are read. If a port H read is performed while PHDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PH3 to PH0. Rev. 3.00 Mar 17, 2006 page 518 of 926 REJ09B0283-0300 Section 10 I/O Ports 10.16.4 Pin Functions Port H pins also function as bus control signal I/Os and external interrupt inputs. The correspondence between the register specification and the pin functions is shown below. * PH3/CS7/OE/CKE* /(IRQ7) 2 The pin function is switched as shown below according to the operating mode, bit EXPE, bit OEE, bit OES, bit CS7E, and bit PH3DDR. Operating mode EXPE CEE CES Area 2 to 5 0 -- -- 0 -- 1, 2, 4, 5, 6 3*2, 7 -- 1 1 Normal synspace chronous or DRAM DRAM space*2 space 1 1 0 1 -- -- -- -- CKE*2 output 0 0 -- -- -- 0 0 -- 1 1 1 -- Normal synspace chronous or DRAM DRAM space*2 space 1 1 0 1 -- -- -- -- CKE*2 output CS7E PH3DDR Pin function 0 0 1 0 1 1 0 0 -- 1 0 0 1 0 1 1 0 0 PH3 PH3 PH3 CS7 PH3 PH3 PH3 CS7 OE input output input output input output input output output PH3 PH3 PH3 PH3 PH3 CS7 PH3 PH3 PH3 CS7 OE input output input output input output input output input output output IRQ7 input*1 Notes: 1. IRQ7 interrupt input pin when bit ITS7 is set to 1 in ITSR 2. Only in H8S/2678R Group. * PH2/CS6/(IRQ6) The pin function is switched as shown below according to the operating mode, bit PH2DDR, and bit CS6E. Operating mode EXPE CS6E PH2DDR Pin function 0 PH2 input 0 1 PH2 output 0 PH2 input 1, 2, 4, 5, 6 -- 1 1 CS6 output 0 PH2 input 0 -- 1 PH2 output 0 PH2 input 0 1 PH2 output 0 PH2 input 3*2, 7 1 1 1 CS6 output IRQ6 interrupt input*1 Notes: 1. IRQ6 interrupt input pin when bit ITS6 is set to 1 in ITSR. 2. Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 519 of 926 REJ09B0283-0300 Section 10 I/O Ports * PH1/CS5/RAS5*/SDRAM* The pin function is switched as shown below according to the operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR. Operating mode EXPE Area 5 DCTL CS5E PH1DDR Pin function 0 0 1 0 1 1 0 0 1 1 -- 0 Normal space 1, 2, 4, 5, 6 3*, 7 -- -- DRAM space 0 -- 0 -- 1 0 0 1 0 1 Normal space 1 DRAM space -- -- 1 0 1 1 -- -- -- 1 0 PH1 PH1 PH1 CS5 PH1 PH1 RAS5* input output input output input output output PH1 PH1 PH1 PH1 PH1 CS5 PH1 PH1 RAS5* SDRAM* input output input output input output input output output output Note: * Only in H8S/2678R Group. * PH0/CS4/RAS4*/WE* The pin function is switched as shown below according to the operating mode, bit EXPE, bit CS4E, bits RMTS2 to RMTS0, and bit PH0DDR. Operating mode EXPE Area 4 -- 1, 2, 4, 5, 6 3*, 7 -- Normal space DRAM space Synchronous DRAM* space 0 -- -- 1 Normal space DRAM space Synchronous DRAM* space SC4E PH1DDR Pin function 0 PH0 input 0 1 PH0 output 0 PH0 input 1 CS4 output 1 -- RAS4* output -- WE* output 0 PH0 input -- 1 PH0 output 0 PH0 input 0 1 PH0 output 0 PH0 input 1 CS4 output 1 -- RAS4* output -- WE* output Note: * Only in H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 520 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure 11.1, respectively. 11.1 Features * Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operations: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated * A/D converter conversion start trigger can be generated * Module stop mode can be set TIMTPU0A_010020020400 Rev. 3.00 Mar 17, 2006 page 521 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.1 TPU Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGRA_1 TGRB_1 -- TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 -- TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGRA_4 TGRB_4 -- TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 -- TIOCA5 TIOCB5 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation -- -- -- -- -- -- Rev. 3.00 Mar 17, 2006 page 522 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 TGR compare match or input capture TGRA_1 compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture 4 sources Channel 2 TGR compare match or input capture TGRA_2 compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture 4 sources Channel 3 TGR compare match or input capture TGRA_3 compare match or input capture TGRA_3 compare match or input capture Channel 4 TGR compare match or input capture TGRA_4 compare match or input capture TGRA_4 compare match or input capture Channel 5 TGR compare match or input capture TGRA_5 compare match or input capture TGRA_5 compare match or input capture -- DTC TGR activation compare match or input capture DMAC TGRA_0 activation compare match or input capture A/D TGRA_0 converter compare trigger match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture 5 sources TGRA_3/ -- TGRB_3 compare match or input capture 5 sources 4 sources Interrupt sources 4 sources * Compare * Compare * Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture 0A capture 1A capture 2A capture 3A capture 4A capture 5A Compare * Compare * Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture 0B capture 1B capture 2B capture 3B capture 4B capture 5B * Compare * Overflow match or * Underflow input capture 0C * Compare match or input capture 0D * Overflow * Overflow * Underflow * Compare * Overflow match or * Underflow input capture 3C * Compare match or input capture 3D * Overflow * Overflow * Underflow Legend: : Possible -- : Not possible Rev. 3.00 Mar 17, 2006 page 523 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TGRA TIOR TMDR Channel 2 TSR Clock input Internal clock: /1 /4 /16 /64 /256 /1024 /4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TGRA TIOR TMDR TSR TIER TCR TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal PPG output trigger signal TGRA TIOR TIER TCR TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 Channel 2: TIOCA2 TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: TSR: TGR (A, B, C, D): TCNT: TIER TCR Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 11.1 Block Diagram of TPU Rev. 3.00 Mar 17, 2006 page 524 of 926 REJ09B0283-0300 TGRA Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.2 Pin Configuration Channel All Symbol TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin Rev. 3.00 Mar 17, 2006 page 525 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3 Register Descriptions The TPU has the following registers in each channel. * Timer control register_0 (TCR_0) * Timer mode register_0 (TMDR_0) * Timer I/O control register H_0 (TIORH_0) * Timer I/O control register L_0 (TIORL_0) * Timer interrupt enable register_0 (TIER_0) * Timer status register_0 (TSR_0) * Timer counter_0 (TCNT_0) * Timer general register A_0 (TGRA_0) * Timer general register B_0 (TGRB_0) * Timer general register C_0 (TGRC_0) * Timer general register D_0 (TGRD_0) * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register _1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) * Timer control register_3 (TCR_3) * Timer mode register_3 (TMDR_3) * Timer I/O control register H_3 (TIORH_3) * Timer I/O control register L_3 (TIORL_3) Rev. 3.00 Mar 17, 2006 page 526 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) * Timer interrupt enable register_3 (TIER_3) * Timer status register_3 (TSR_3) * Timer counter_3 (TCNT_3) * Timer general register A_3 (TGRA_3) * Timer general register B_3 (TGRB_3) * Timer general register C_3 (TGRC_3) * Timer general register D_3 (TGRD_3) * Timer control register_4 (TCR_4) * Timer mode register_4 (TMDR_4) * Timer I/O control register _4 (TIOR_4) * Timer interrupt enable register_4 (TIER_4) * Timer status register_4 (TSR_4) * Timer counter_4 (TCNT_4) * Timer general register A_4 (TGRA_4) * Timer general register B_4 (TGRB_4) * Timer control register_5 (TCR_5) * Timer mode register_5 (TMDR_5) * Timer I/O control register_5 (TIOR_5) * Timer interrupt enable register_5 (TIER_5) * Timer status register_5 (TSR_5) * Timer counter_5 (TCNT_5) * Timer general register A_5 (TGRA_5) * Timer general register B_5 (TGRB_5) Common Registers * Timer start register (TSTR) * Timer synchronous register (TSYR) Rev. 3.00 Mar 17, 2006 page 527 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 11.3 and 11.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges Legend: x: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 11.5 to 11.10 for details. Rev. 3.00 Mar 17, 2006 page 528 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3) Channel 0, 3 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 0 0 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel 1, 2, 4, 5 Bit 6 Bit 7 2 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 529 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.5 TPSC2 to TPSC0 (Channel 0) Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 11.6 TPSC2 to TPSC0 (Channel 1) Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 3.00 Mar 17, 2006 page 530 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.7 TPSC2 to TPSC0 (Channel 2) Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 11.8 TPSC2 to TPSC0 (Channel 3) Channel 3 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096 Rev. 3.00 Mar 17, 2006 page 531 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.9 TPSC2 to TPSC0 (Channel 4) Channel 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 11.10 TPSC2 to TPSC0 (Channel 5) Channel 5 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 3.00 Mar 17, 2006 page 532 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit 7, 6 Bit Name -- Initial Value All 1 R/W -- Description Reserved These bits are always read as 1 and cannot be modified. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. MD3 is a reserved bit. In a write, it should always be written with 0. See table 11.11 for details. Rev. 3.00 Mar 17, 2006 page 533 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.11 MD3 to MD0 Bit 3 1 MD3* 0 Bit 2 2 MD2* 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 x x x Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- Legend: x: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 11.3.3 Timer I/O Control Register (TIOR) TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 3.00 Mar 17, 2006 page 534 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Initial Value Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. For details, see tables 11.12, 11.14, 11.15, 11.16, 11.18, and 11.19. I/O Control A3 to A0 Specify the function of TGRA. For details, see tables 11.20, 11.22, 11.23, 11.24, 11.26, and 11.27. TIORL_0, TIORL_3 Initial Value Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control D3 to D0 Specify the function of TGRD. For details, see tables 11.13, and 11.17. I/O Control C3 to C0 Specify the function of TGRC. For details, see tables 11.21, and 11.25 Rev. 3.00 Mar 17, 2006 page 535 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.12 TIORH_0 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down* Legend: x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 3.00 Mar 17, 2006 page 536 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.13 TIORL_0 Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture 2 register* TGRD_0 Function Output compare 2 register* TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 Legend: x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Mar 17, 2006 page 537 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.14 TIOR_1 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 538 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.15 TIOR_2 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges Rev. 3.00 Mar 17, 2006 page 539 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.16 TIORH_3 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge Capture input source is TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* Legend: x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev. 3.00 Mar 17, 2006 page 540 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.17 TIORL_3 Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture 2 register* TGRD_3 Function Output compare 2 register* TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge Capture input source is TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 Legend: x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Mar 17, 2006 page 541 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.18 TIOR_4 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge Capture input source is TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 542 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.19 TIOR_5 Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge Capture input source is TIOCB5 pin Input capture at both edges Rev. 3.00 Mar 17, 2006 page 543 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.20 TIORH_0 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 544 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.21 TIORL_0 Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge Capture input source is TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: x: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Mar 17, 2006 page 545 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.22 TIOR_1 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 546 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.23 TIOR_2 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges Rev. 3.00 Mar 17, 2006 page 547 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.24 TIORH_3 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge Capture input source is TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 548 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.25 TIORL_3 Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_3 Function Output compare register* TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge Capture input source is TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down Legend: x: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 3.00 Mar 17, 2006 page 549 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.26 TIOR_4 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge Capture input source is TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture Legend: x: Don't care Rev. 3.00 Mar 17, 2006 page 550 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.27 TIOR_5 Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge Input capture source is TIOCA5 pin Input capture at both edges Rev. 3.00 Mar 17, 2006 page 551 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 -- TCIEU 1 0 -- R/W Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 3.00 Mar 17, 2006 page 552 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGIEC Initial value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 3.00 Mar 17, 2006 page 553 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5 -- TCFU 1 0 -- R/(W)* Reserved This bit is always read as 1 and cannot be modified. Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 3.00 Mar 17, 2006 page 554 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value 0 R/W R/(W)* Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1 [Clearing conditions] * * 2 TGFC 0 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1 [Clearing conditions] * * Rev. 3.00 Mar 17, 2006 page 555 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value 0 R/W R/(W)* Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB = 1 [Clearing conditions] * * 0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA = 1 [Clearing conditions] * * Note: * Only 0 can be written, for flag clearing. Rev. 3.00 Mar 17, 2006 page 556 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.7 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA-TGRC and TGRB-TGRD. 11.3.8 Timer Start Register (TSTR) TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7, 6 5 4 3 2 1 0 Bit Name -- CST5 CST4 CST3 CST2 CST1 CST0 Initial value All 0 0 0 0 0 0 0 R/W -- R/W R/W R/W R/W R/W R/W Description Reserved These bits should always be written with 0. Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev. 3.00 Mar 17, 2006 page 557 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7, 6 5 4 3 2 1 0 Bit Name -- SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits should always be written with 0. Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 performs synchronous operation (TCNT synchronous presetting/ synchronous clearing is possible) Rev. 3.00 Mar 17, 2006 page 558 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4 11.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. 1. Example of count operation setting procedure Figure 11.2 shows an example of the count operation setting procedure. Operation selection [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count Select counter clock [1] Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] Figure 11.2 Example of Counter Operation Setting Procedure Rev. 3.00 Mar 17, 2006 page 559 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 11.3 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 11.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 11.4 illustrates periodic counter operation. Rev. 3.00 Mar 17, 2006 page 560 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 11.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. 1. Example of setting procedure for waveform output by compare match Figure 11.5 shows an example of the setting procedure for waveform output by a compare match. Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match Rev. 3.00 Mar 17, 2006 page 561 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 11.6 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 11.6 Example of 0 Output/1 Output Operation Figure 11.7 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 11.7 Example of Toggle Output Operation Rev. 3.00 Mar 17, 2006 page 562 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. 1. Example of setting procedure for input capture operation Figure 11.8 shows an example of the setting procedure for input capture operation. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [1] Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 11.8 Example of Setting Procedure for Input Capture Operation Rev. 3.00 Mar 17, 2006 page 563 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 11.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 11.9 Example of Input Capture Operation 11.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Rev. 3.00 Mar 17, 2006 page 564 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure: Figure 11.10 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source No [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 11.10 Example of Synchronous Operation Setting Procedure Rev. 3.00 Mar 17, 2006 page 565 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 11.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 11.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 11.11 Example of Synchronous Operation 11.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 11.28 shows the register combinations used in buffer operation. Rev. 3.00 Mar 17, 2006 page 566 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.28 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.12. Compare match signal Buffer register Timer general register Comparator TCNT Figure 11.12 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11.13. Input capture signal Timer general register Buffer register TCNT Figure 11.13 Input Capture Buffer Operation Rev. 3.00 Mar 17, 2006 page 567 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure: Figure 11.14 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Buffer operation Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 11.14 Example of Buffer Operation Setting Procedure Rev. 3.00 Mar 17, 2006 page 568 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 11.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 11.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 11.15 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 11.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 3.00 Mar 17, 2006 page 569 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 11.16 Example of Buffer Operation (2) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.29 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 11.29 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5 Rev. 3.00 Mar 17, 2006 page 570 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Start count [2] Figure 11.17 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGRA_2 H'0000 Figure 11.18 Example of Cascaded Operation (1) Rev. 3.00 Mar 17, 2006 page 571 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 11.19 Example of Cascaded Operation (2) 11.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. Rev. 3.00 Mar 17, 2006 page 572 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.30. Table 11.30 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev. 3.00 Mar 17, 2006 page 573 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] PWM mode Select counter clock [1] Select waveform output level [3] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGRs. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 11.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 11.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as the duty cycle. Rev. 3.00 Mar 17, 2006 page 574 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 11.21 Example of PWM Mode Operation (1) Figure 11.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 11.22 Example of PWM Mode Operation (2) Rev. 3.00 Mar 17, 2006 page 575 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 11.23 Example of PWM Mode Operation (3) Rev. 3.00 Mar 17, 2006 page 576 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 11.31 shows the correspondence between external clock pins and channels. Table 11.31 Clock Input Pins in Phase Counting Mode External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 11.24 shows an example of the phase counting mode setting procedure. Phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [1] Select phase counting mode Start count [2] Figure 11.24 Example of Phase Counting Mode Setting Procedure Rev. 3.00 Mar 17, 2006 page 577 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 11.25 shows an example of phase counting mode 1 operation, and table 11.32 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.25 Example of Phase Counting Mode 1 Operation Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 3.00 Mar 17, 2006 page 578 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 11.26 shows an example of phase counting mode 2 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.26 Example of Phase Counting Mode 2 Operation Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count Up-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Rev. 3.00 Mar 17, 2006 page 579 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 11.27 shows an example of phase counting mode 3 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.27 Example of Phase Counting Mode 3 Operation Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Up-count Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Rev. 3.00 Mar 17, 2006 page 580 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 11.28 shows an example of phase counting mode 4 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.28 Example of Phase Counting Mode 4 Operation Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 3.00 Mar 17, 2006 page 581 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 11.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function, and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 + + - TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 11.29 Phase Counting Mode Application Example Rev. 3.00 Mar 17, 2006 page 582 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.5 Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 11.36 lists the TPU interrupt sources. Rev. 3.00 Mar 17, 2006 page 583 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.36 TPU Interrupts Channel 0 Name TGI0A TGI0B TGI0C TGI0D TGI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5 DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible DMAC Activation Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 3.00 Mar 17, 2006 page 584 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 11.6 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 9, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 11.7 DMAC Activation The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. 11.8 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev. 3.00 Mar 17, 2006 page 585 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 11.9 11.9.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 11.30 shows TCNT count timing in internal clock operation, and figure 11.31 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 11.30 Count Timing in Internal Clock Operation External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 11.31 Count Timing in External Clock Operation Rev. 3.00 Mar 17, 2006 page 586 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated. Figure 11.32 shows output compare output timing. TCNT input clock N N+1 TCNT TGR N Compare match signal TIOC pin Figure 11.32 Output Compare Output Timing Input Capture Signal Timing: Figure 11.33 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 11.33 Input Capture Input Signal Timing Rev. 3.00 Mar 17, 2006 page 587 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.35 shows the timing when counter clearing by input capture occurrence is specified. Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 11.34 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 11.35 Counter Clear Timing (Input Capture) Rev. 3.00 Mar 17, 2006 page 588 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 11.36 and 11.37 show the timings in buffer operation. TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 11.36 Buffer Operation Timing (Compare Match) Input capture signal TCNT N N+1 TGRA, TGRB TGRC, TGRD n N N+1 n N Figure 11.37 Buffer Operation Timing (Input Capture) Rev. 3.00 Mar 17, 2006 page 589 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 11.38 TGI Interrupt Timing (Compare Match) Rev. 3.00 Mar 17, 2006 page 590 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 11.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Input Capture) Rev. 3.00 Mar 17, 2006 page 591 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 11.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 11.40 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 11.41 TCIU Interrupt Setting Timing Rev. 3.00 Mar 17, 2006 page 592 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42 shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 11.42 Timing for Status Flag Clearing by CPU DTC/DMAC read cycle T1 T2 DTC/DMAC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation Rev. 3.00 Mar 17, 2006 page 593 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.44 shows the input clock conditions in phase counting mode. Phase Phase diffediffeOverlap rence rence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 3.00 Mar 17, 2006 page 594 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= (N + 1) Where f: Counter frequency : Operating frequency N: TGR set value 11.10.4 Contention between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.45 shows the timing in this case. TCNT write cycle T1 T2 Address TCNT address Write signal Counter clearing signal TCNT N H'0000 Figure 11.45 Contention between TCNT Write and Clear Operations Rev. 3.00 Mar 17, 2006 page 595 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.46 shows the timing in this case. TCNT write cycle T1 T2 Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 11.46 Contention between TCNT Write and Increment Operations Rev. 3.00 Mar 17, 2006 page 596 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.47 shows the timing in this case. TGR write cycle T1 T2 Address TGR address Write signal Compare match signal TCNT N N+1 Prohibited TGR N TGR write data M Figure 11.47 Contention between TGR Write and Compare Match Rev. 3.00 Mar 17, 2006 page 597 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.48 shows the timing in this case. TGR write cycle T1 T2 Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.48 Contention between Buffer Register Write and Compare Match Rev. 3.00 Mar 17, 2006 page 598 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.49 shows the timing in this case. TGR read cycle T1 T2 Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 11.49 Contention between TGR Read and Input Capture Rev. 3.00 Mar 17, 2006 page 599 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.50 shows the timing in this case. TGR write cycle T1 T2 Address TGR address Write signal Input capture signal TCNT M TGR M Figure 11.50 Contention between TGR Write and Input Capture Rev. 3.00 Mar 17, 2006 page 600 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.51 shows the timing in this case. Buffer register write cycle T1 T2 Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 11.51 Contention between Buffer Register Write and Input Capture Rev. 3.00 Mar 17, 2006 page 601 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. TCNT input clock TCNT Counter clearing signal TGF Prohibited TCFV H'FFFF H'0000 Figure 11.52 Contention between Overflow and Counter Clearing Rev. 3.00 Mar 17, 2006 page 602 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.53 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 Address TCNT address Write signal TCNT write data H'FFFF Prohibited M TCNT TCFV flag Figure 11.53 Contention between TCNT Write and Overflow 11.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 11.10.14 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 3.00 Mar 17, 2006 page 603 of 926 REJ09B0283-0300 Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Mar 17, 2006 page 604 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1 12.1 Features * 16-bit output data * Four output groups * Selectable output trigger signals * Non-overlap mode * Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC) * Settable inverted output * Module stop mode can be set PPG0001A_000020020400 Rev. 3.00 Mar 17, 2006 page 605 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus Legend: PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Figure 12.1 Block Diagram of PPG Rev. 3.00 Mar 17, 2006 page 606 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.2 Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 0 pulse output Group 1 pulse output Group 2 pulse output Function Group 3 pulse output 12.3 Register Descriptions The PPG has the following registers. * Next data enable register H (NDERH) * Next data enable register L (NDERL) * Output data register H (PODRH) * Output data register L (PODRL) * Next data register H (NDRH) * Next data register L (NDRL) * PPG output control register (PCR) * PPG output mode register (PMR) Rev. 3.00 Mar 17, 2006 page 607 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1. NDERH Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 15 to 8 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. NDERL Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. Rev. 3.00 Mar 17, 2006 page 608 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. PODRH Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 15 to 8 For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. PODRL Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. Rev. 3.00 Mar 17, 2006 page 609 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR15 NDR14 NDR13 NDR12 -- Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W -- Description Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 610 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 1 R/W -- Description Reserved These bits are always read as 1 and cannot be modified. NDR11 NDR10 NDR9 NDR8 0 0 0 0 R/W R/W R/W R/W Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Bit 7 6 5 4 3 to 0 Bit Name NDR7 NDR6 NDR5 NDR4 -- Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W -- Description Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 611 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Bit 7 to 4 3 2 1 0 Bit Name -- Initial Value All 1 R/W -- Description Reserved These bits are always read as 1 and cannot be modified. NDR3 NDR2 NDR1 NDR0 0 0 0 0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 12.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 3 Compare Match Select 1 and 0 Select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 2 Compare Match Select 1 and 0 Select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 2 G1CMS1 G1CMS0 1 1 R/W R/W Group 1 Compare Match Select 1 and 0 Select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 Rev. 3.00 Mar 17, 2006 page 612 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Bit 1 0 Bit Name G0CMS1 G0CMS0 Initial Value 1 1 R/W R/W R/W Description Group 0 Compare Match Select 1 and 0 Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 12.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping Pulse Output. Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5 G1INV 1 R/W Group 1 Inversion Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output Rev. 3.00 Mar 17, 2006 page 613 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Bit 4 Bit Name G0INV Initial Value 1 R/W R/W Description Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 1 G1NOV 0 R/W Group 1 Non-Overlap Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 0 G0NOV 0 R/W Group 0 Non-Overlap Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) Rev. 3.00 Mar 17, 2006 page 614 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4 Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. DDR NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 12.2 Overview Diagram of PPG Rev. 3.00 Mar 17, 2006 page 615 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 TGRA N Compare match A signal NDRH n PODRH m n PO8 to PO15 m n Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) Rev. 3.00 Mar 17, 2006 page 616 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.2 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output compare register (with output disabled) [2] Set the PPG output trigger period Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Port and PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [2] Normal PPG output Select TGR functions [1] [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. [8] [9] No Figure 12.4 Setup Procedure for Normal Pulse Output (Example) Rev. 3.00 Mar 17, 2006 page 617 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TGRA Compare match TCNT H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88, ... at successive TGIA interrupts. Rev. 3.00 Mar 17, 2006 page 618 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. 12.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: * NDR bits are always transferred to PODR bits at compare match A. * At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 12.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs. Figure 12.7 shows the timing of this operation. Rev. 3.00 Mar 17, 2006 page 619 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here Write to NDR Do not write here to NDR here Do not write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Rev. 3.00 Mar 17, 2006 page 620 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping pulse output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match A? Yes Set next pulse output data [11] [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) [2] Set the pulse output trigger period in TGRB and the non-overlap period in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR2 to CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. PPG setup [9] [10] No Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 3.00 Mar 17, 2006 page 621 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) Rev. 3.00 Mar 17, 2006 page 622 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95, ... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 3.00 Mar 17, 2006 page 623 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.10 Inverted Pulse Output (Example) Rev. 3.00 Mar 17, 2006 page 624 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) 12.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. TIOC pin Input capture signal NDR N PODR M N PO M N Figure 12.11 Pulse Output Triggered by Input Capture (Example) 12.5 12.5.1 Usage Notes Module Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 12.5.2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev. 3.00 Mar 17, 2006 page 625 of 926 REJ09B0283-0300 Section 12 Programmable Pulse Generator (PPG) Rev. 3.00 Mar 17, 2006 page 626 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.1 Features * Selection of four clock sources The counters can be driven by one of three internal clock signals (/8, /64, or /8192) or an external clock input * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output * Provision for cascading of two channels (TMR_0 and TMR_1) Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode) TMR_1 can be used to count TMR_0 compare matches (compare match count mode) * Three independent interrupts Compare match A and B and overflow interrupts can be requested independently * A/D converter conversion start trigger can be generated TIMH260A_000020020400 Rev. 3.00 Mar 17, 2006 page 627 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). External clock source TMCI0 TMCI1 Internal clock sources TMR_0 TMR_1 /8 /8 /64 /64 /8192 /8192 Clock select Clock 1 Clock 0 TCORA_0 Compare match A1 Compare match A0 Comparator A_0 TCORA_1 Comparator A_1 TMO0 TMRI0 Overflow 1 Overflow 0 Clear 0 TCNT_0 Clear 1 TCNT_1 Internal bus TMO1 TMRI1 Control logic Compare match B1 Compare match B0 Comparator B_0 Comparator B_1 TCORB_0 A/D conversion start request signal TCORB_1 TCSR_0 TCSR_1 TCR_0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals Legend: TCORA_0 TCORB_0 TCNT_0 TCSR_0 TCR_0 : Time constant register A_0 : Time constant register B_0 : Timer counter_0 : Timer control/status register_0 : Timer control register_0 TCORA_1 TCORB_1 TCNT_1 TCSR_1 TCR_1 TCR_1 : Time constant register A_1 : Time constant register B_1 : Timer counter_1 : Timer control/status register_1 : Timer control register_1 Figure 13.1 Block Diagram of 8-Bit Timer Module Rev. 3.00 Mar 17, 2006 page 628 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer. Table 13.1 Pin Configuration Channel 0 Name Timer output pin Timer clock input pin Timer reset input pin 1 Timer output pin Timer clock input pin Timer reset input pin Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Outputs at compare match Inputs external clock for counter Inputs external reset to counter Outputs at compare match Inputs external clock for counter Inputs external reset to counter 13.3 Register Descriptions The 8-bit timer module has the following registers. For details on the module stop control register, refer to section 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL). * Timer counter_0 (TCNT_0) * Time constant register A_0 (TCORA_0) * Time constant register B_0 (TCORB_0) * Timer control register_0 (TCR_0) * Timer control/status register_0 (TCSR_0) * Timer counter_1 (TCNT_1) * Time constant register A_1 (TCORA_1) * Time constant register B_1 (TCORB_1) * Timer control register_1 (TCR_1) * Timer control/status register_1 (TCSR_1) Rev. 3.00 Mar 17, 2006 page 629 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.3.1 Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00. 13.3.2 Time Constant Register A (TCORA) TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 13.3.3 Time Constant Register B (TCORB) TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOBR write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. Rev. 3.00 Mar 17, 2006 page 630 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled 6 CMIEA 0 R/W Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 These bits select the method by which TCNT is cleared 00: Clearing is disabled 01: Clear by compare match A 10: Clear by compare match B 11: Clear by rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and count condition. See table 13.2. Rev. 3.00 Mar 17, 2006 page 631 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Table 13.2 Clock Input to TCNT and Count Condition TCR Channel TMR_0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 TMR_1 0 0 0 0 0 1 1 0 1 1 All 1 0 0 1 1 Note: * 0 1 0 1 Description Clock input disabled Internal clock, counted at falling edge of /8 Internal clock, counted at falling edge of /64 Internal clock, counted at falling edge of /8192 Count at TCNT_1 overflow signal* Clock input disabled Internal clock, counted at falling edge of /8 Internal clock, counted at falling edge of /64 Internal clock, counted at falling edge of /8192 Count at TCNT_0 compare match A* External clock, counted at rising edge External clock, counted at falling edge External clock, counted at both rising and falling edges If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. Rev. 3.00 Mar 17, 2006 page 632 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output. TCSR_0 Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare Match Flag B [Setting condition] Set when TCNT matches TCORB [Clearing conditions] * * 6 CMFA 0 R/(W)* Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] Set when TCNT matches TCORA [Clearing conditions] * * Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 ADTE 0 R/W A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled Rev. 3.00 Mar 17, 2006 page 633 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Bit 3 2 Bit Name OS3 OS2 Initial Value 0 0 R/W R/W R/W Description Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev. 3.00 Mar 17, 2006 page 634 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) TCSR_1 Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare Match Flag B [Setting condition] Set when TCNT matches TCORB [Clearing conditions] * * 6 CMFA 0 R/(W)* Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] Set when TCNT matches TCORA [Clearing conditions] * * Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 -- 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 635 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Bit 3 2 Bit Name OS3 OS2 Initial Value 0 0 R/W R/W R/W Description Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: * Only 0 can be written to bits 7 to 5, to clear these flags. 13.4 13.4.1 Operation Pulse Output Figure 13.2 shows an example that the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared at a TCORA compare match. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. Rev. 3.00 Mar 17, 2006 page 636 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 13.2 Example of Pulse Output 13.5 13.5.1 Operation Timing TCNT Incrementation Timing Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock Clock input to TCNT TCNT N-1 N N+1 Figure 13.3 Count Timing for Internal Clock Input Rev. 3.00 Mar 17, 2006 page 637 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) External clock input pin Clock input to TCNT TCNT N-1 N N+1 Figure 13.4 Count Timing for External Clock Input 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 13.5 shows this timing. TCNT N N+1 TCOR Compare match signal N CMF Figure 13.5 Timing of CMF Setting Rev. 3.00 Mar 17, 2006 page 638 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.5.3 Timing of Timer Output when Compare-Match Occurs When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.6 shows the timing when the output is set to toggle at compare match A. Compare match A signal Timer output pin Figure 13.6 Timing of Timer Output 13.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.7 shows the timing of this operation. Compare match signal TCNT N H'00 Figure 13.7 Timing of Compare Match Clear Rev. 3.00 Mar 17, 2006 page 639 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.8 shows the timing of this operation. External reset input pin Clear signal TCNT N-1 N H'00 Figure 13.8 Timing of Clearance by External Reset 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.9 shows the timing of this operation. TCNT H'FF H'00 Overflow signal OVF Figure 13.9 Timing of OVF Setting Rev. 3.00 Mar 17, 2006 page 640 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.1 16-Bit Counter Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. [1] Setting of compare match flags * The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. [2] Counter clear specification * If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter clear by the TMRI0 pin has also been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. [3] Pin output * Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions. * Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions. 13.6.2 Compare Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A's for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Rev. 3.00 Mar 17, 2006 page 641 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.7 13.7.1 Interrupts Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 13.3 8-Bit Timer Interrupt Sources Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt Source TCORA_0 compare match TCORB_0 compare match TCNT_0 overflow TCORA_1 compare match TCORB_1 compare match TCNT_1 overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Low High Priority High 13.7.2 A/D Converter Activation The A/D converter can be activated only by TMR_0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev. 3.00 Mar 17, 2006 page 642 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.8 13.8.1 Usage Notes Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.10 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.10 Contention between TCNT Write and Clear Rev. 3.00 Mar 17, 2006 page 643 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.11 shows this operation. TCNT write cycle by CPU T1 T2 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.11 Contention between TCNT Write and Increment Rev. 3.00 Mar 17, 2006 page 644 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.8.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.12. TCOR write cycle by CPU T1 T2 Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 13.12 Contention between TCOR Write and Compare Match Rev. 3.00 Mar 17, 2006 page 645 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) 13.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.4. Table 13.4 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 13.8.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 13.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks. Rev. 3.00 Mar 17, 2006 page 646 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Table 13.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from 1 low to low* Clock before switchover Clock after switchover TCNT clock No. 1 TCNT N CKS bit write N+1 2 Switching from 2 low to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from 3 high to low* Clock before swichover Clock after swichover *4 TCNT clock TCNT N N+1 CKS bit write N+2 Rev. 3.00 Mar 17, 2006 page 647 of 926 REJ09B0283-0300 Section 13 8-Bit Timers (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock No. 4 TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 13.8.6 Mode Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter and compare match count modes simultaneously. 13.8.7 Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 3.00 Mar 17, 2006 page 648 of 926 REJ09B0283-0300 Section 14 Watchdog Timer Section 14 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 14.1. 14.1 Features * Selectable from eight counter input clocks * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode * If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire chip is reset at the same time. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (WOVI). WDT0101A_010020020400 Rev. 3.00 Mar 17, 2006 page 649 of 926 REJ09B0283-0300 Section 14 Watchdog Timer Overflow WOVI (interrupt request signal) WDTOVF Internal reset signal* Interrupt control Clock Clock select Reset control /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources Internal bus RSTCSR TCNT TSCR Bus interface Module bus WDT Legend: : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 14.1 Block Diagram of WDT 14.2 Input/Output Pin Table 14.1 shows the WDT pin configuration. Table 14.1 Pin configuration Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs counter overflow signal in watchdog timer mode 14.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) Rev. 3.00 Mar 17, 2006 page 650 of 926 REJ09B0283-0300 Section 14 Watchdog Timer 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* Description Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. Rev. 3.00 Mar 17, 2006 page 651 of 926 REJ09B0283-0300 Section 14 Watchdog Timer Bit 4, 3 Bit Name -- Initial Value All 1 R/W -- Description Reserved These bits are always read as 1 and cannot be modified. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) Note: * Only a write of 0 is permitted, to clear the flag. Rev. 3.00 Mar 17, 2006 page 652 of 926 REJ09B0283-0300 Section 14 Watchdog Timer 14.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W)* Description Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF 6 RSTE 0 R/W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 -- 0 R/W Reserved Can be read and written, but does not affect operation. 4 to 0 Note: -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. * Only a write of 0 is permitted, to clear the flag. Rev. 3.00 Mar 17, 2006 page 653 of 926 REJ09B0283-0300 Section 14 Watchdog Timer 14.4 14.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer mode. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. The internal reset signal is output for 518 states. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the entire chip. Rev. 3.00 Mar 17, 2006 page 654 of 926 REJ09B0283-0300 Section 14 Watchdog Timer TCNT count Overflow H'FF H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT Time WDTOVF signal 132 states*2 Internal reset signal*1 518 states Legend: WT/IT : Timer mode select bit TME : Timer enable bit Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode 14.4.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. Rev. 3.00 Mar 17, 2006 page 655 of 926 REJ09B0283-0300 Section 14 Watchdog Timer TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 14.3 Operation in Interval Timer Mode 14.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 14.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible 14.6 14.6.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Rev. 3.00 Mar 17, 2006 page 656 of 926 REJ09B0283-0300 Section 14 Watchdog Timer Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0 to the WOVF bit, satisfy the lower condition shown in figure 14.4. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, satisfy the above condition shown in figure 14.4. If satisfied, the transfer instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit. TCNT write or Writing to RSTE bit in RSTCSR 15 Address: H'FFBC (TCNT) H'FFBE (RSTCSR) TCSR write Address: H'FFBC (TCSR) 15 H'A5 8 7 Write data 0 8 H'5A 7 Write data 0 Writing 0 to WOVF bit in RSTCSR Address: H'FFBE (RSTCSR) 15 H'A5 8 7 H'00 0 Figure 14.4 Writing to TCNT, TCSR, and RSTCSR Reading TCNT, TCSR, and RSTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. Rev. 3.00 Mar 17, 2006 page 657 of 926 REJ09B0283-0300 Section 14 Watchdog Timer 14.6.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 T2 Next cycle Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.5 Contention between TCNT Write and Increment 14.6.3 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 3.00 Mar 17, 2006 page 658 of 926 REJ09B0283-0300 Section 14 Watchdog Timer 14.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 14.6.6 System Reset by WDTOVF Signal If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6. This LSI Reset input RES Reset signal to entire system WDTOVF Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) Rev. 3.00 Mar 17, 2006 page 659 of 926 REJ09B0283-0300 Section 14 Watchdog Timer Rev. 3.00 Mar 17, 2006 page 660 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an asynchronous serial communication interface extension function. One of the three SCI channels (SCI_0) can generate an IrDA communication waveform conforming to IrDA specification version 1.0. Figure 15.1 shows a block diagram of the SCI. 15.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources -- transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC). * Module stop mode can be set Asynchronous mode * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors SCI0020A_000020020400 Rev. 3.00 Mar 17, 2006 page 661 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) * Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Average transfer rate generator (only for H8S/2678R Group): The following transfer rate can be selected (SCI_2 only) 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.784 or 720 kbps at 16-MHz operation 720 kbps at 32-MHz operation Clocked Synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card Interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported Rev. 3.00 Mar 17, 2006 page 662 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR SEMR* Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI Legend: RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register SCMR : Smart card mode register BRR : Bit rate register SEMR : Serial extension mode register (only in SCI_2) Note: * Only in H8S/2678R Group. Average transfer rate generator* (SCI_2) 10.667-MHz operation * 115.152 kbps * 460.606 kbps 16-MHz operation * 115.196 kbps * 460.784 kbps * 720 kbps 32-MHz operation * 720 kbps Figure 15.1 Block Diagram of SCI Rev. 3.00 Mar 17, 2006 page 663 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the serial communication interface. Table 15.1 Pin Configuration Channel 0 Pin Name* SCK0 RxD0/IrRxD TxD0/IrTxD 1 SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 Note: * I/O I/O Input Output I/O Input Output I/O Input Output Function Channel 0 clock input/output Channel 0 receive data input (normal/IrDA) Channel 0 transmit data output (normal/IrDA) Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 15.3 Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ. * Receive shift register_0 (RSR_0) * Transmit shift register_0 (TSR_0) * Receive data register_0 (RDR_0) * Transmit data register_0 (TDR_0) * Serial mode register_0 (SMR_0) * Serial control register_0 (SCR_0) * Serial status register_0 (SSR_0) * Smart card mode register_0 (SCMR_0) * Bit rate register_0 (BRR_0) * IrDA control register_0 (IrCR_0) * Receive shift register_1 (RSR_1) * Transmit shift register_1 (TSR_1) Rev. 3.00 Mar 17, 2006 page 664 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) * Receive data register_1 (RDR_1) * Transmit data register_1 (TDR_1) * Serial mode register_1 (SMR_1) * Serial control register_1 (SCR_1) * Serial status register_1 (SSR_1) * Smart card mode register_1 (SCMR_1) * Bit rate register_1 (BRR_1) * Receive shift register_2 (RSR_2) * Transmit shift register_2 (TSR_2) * Receive data register_2 (RDR_2) * Transmit data register_2 (TDR_2) * Serial mode register_2 (SMR_2) * Serial control register_2 (SCR_2) * Serial status register_2 (SSR_2) * Smart card mode register_2 (SCMR_2) * Bit rate register_2 (BRR_2) * Serial extension mode register (SEMR)* Note: * Only in H8S/2678R Group. 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. Rev. 3.00 Mar 17, 2006 page 665 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot be directly accessed by the CPU. 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock source. Some bit functions of SMR differ in normal serial communication interface mode and Smart Card interface mode. Rev. 3.00 Mar 17, 2006 page 666 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked regardless of the STOP bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit character. Rev. 3.00 Mar 17, 2006 page 667 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0: These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed. For details, refer to section 15.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, refer to section 15.7.3, Block Transfer Mode. Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1. 5 PE 0 R/W Rev. 3.00 Mar 17, 2006 page 668 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 4 Bit Name O/E Initial Value 0 R/W R/W Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on setting this bit in Smart Card interface mode, refer to section 15.7.2, Data Format (Except for Block Transfer Mode). 3 2 BCP1 BCP0 0 0 R/W R/W Basic Clock Pulse 1 and 0 These bits select the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. S stands for the value of S in BRR (see section 15.3.9, Bit Rate Register (BRR)). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Rev. 3.00 Mar 17, 2006 page 669 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.6 Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 15.9, Interrupts Sources. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit s set to 1, transmission is enabled. Receive Enable: When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 15.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. Rev. 3.00 Mar 17, 2006 page 670 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output) 1X: External clock (SCK pin functions as clock input) X: Don't care Rev. 3.00 Mar 17, 2006 page 671 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. Clock Enable 1 and 0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 15.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1X: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output X: Don't care Rev. 3.00 Mar 17, 2006 page 672 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode. Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * * 6 RDRF 0 R/(W)* When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE =1 When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR [Clearing conditions] Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * * When 0 is written to RDRF after reading RDRF = 1 When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. Rev. 3.00 Mar 17, 2006 page 673 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value 0 R/W R/(W)* Description Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 FER 0 R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE =1 When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR [Clearing conditions] * * Rev. 3.00 Mar 17, 2006 page 674 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 1 Bit Name MPB Initial Value 0 R/W R Description Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT sets the multiprocessor bit to be added to the transmit data. Note: * Only 0 can be written, to clear the flag. Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * * 6 RDRF 0 R/(W)* When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE =1 When the DMAC or DTC is activated by a TXI interrupt request and transfers data to TDR [Clearing conditions] Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * * When 0 is written to RDRF after reading RDRF = 1 When the DMAC or DTC is activated by an RXI interrupt and transferred data from RDR The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. Rev. 3.00 Mar 17, 2006 page 675 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value 0 R/W R/(W)* Description Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 ERS 0 R/(W)* Error Signal Status [Setting condition] When the low level of the error signal is sampled [Clearing condition] When 0 is written to ERS after reading ERS = 1 3 PER 0 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 Rev. 3.00 Mar 17, 2006 page 676 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When the TE bit in SCR is 0 and the ERS bit is also 0 If the ERS bit is 0 and the TDRE bit is 1 after the specified interval after transmission of 1byte data Timing to set this bit differs according to the register settings. GM = 0, BLK = 0: 2.5 etu after transmission GM = 0, BLK = 1: 1.5 etu after transmission GM = 1, BLK = 0: 1.0 etu after transmission GM = 1, BLK = 1: 1.0 etu after transmission [Clearing conditions] * * 1 0 Note: MPB MPBT * 0 0 R R/W When 0 is written to TEND after reading TEND =1 When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR Multiprocessor Bit This bit is not used in Smart Card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode. Only 0 can be written, to clear the flag. Rev. 3.00 Mar 17, 2006 page 677 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit 7 to 4 3 Bit Name -- Initial Value All 1 R/W -- Description Reserved These bits are always read as 1. SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 0 -- SMIF 1 0 -- R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode Rev. 3.00 Mar 17, 2006 page 678 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 15.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous Mode Clocked Synchronous Mode Smart Card Interface Mode Bit Rate B= Error x 106 Error (%) = 64 x 22n-1 x (N + 1) x 106 8 x 22n-1 x (N + 1) x 106 Sx 22n+1 x (N + 1) { B x 64 x2x 10x (N + 1) - 1} x 100 6 2n-1 B= B= Error (%) = { B x S x 2 x 10x (N + 1) - 1} x 100 6 2n+1 Note: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following tables. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 SMR Setting BCP0 0 1 0 1 S 32 64 372 256 Rev. 3.00 Mar 17, 2006 page 679 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with external clock input. Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 1 1 0 0 0 0 0 0 -- -- -- 2.097152 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- Rev. 3.00 Mar 17, 2006 page 680 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- Rev. 3.00 Mar 17, 2006 page 681 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 Rev. 3.00 Mar 17, 2006 page 682 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 25 Error (%) -0.02 -0.47 0.15 -0.47 0.15 -0.47 0.15 -0.47 -0.76 0.00 1.73 Operating Frequency (MHz) 30 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 0.16 -0.35 -0.35 0 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0 -0.54 Rev. 3.00 Mar 17, 2006 page 683 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 n 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 (MHz) 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 30 33 Maximum Bit Rate (bit/s) 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 781250 937500 1031250 n 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 (MHz) 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 30 33 External Input Clock (MHz) 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 6.2500 7.5000 8.2500 Maximum Bit Rate (bit/s) 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 390625 468750 515625 Rev. 3.00 Mar 17, 2006 page 684 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M 3 2 1 1 0 0 0 0 0 0 0 0 2 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* 3 2 2 1 0 0 0 0 -- -- -- -- 97 155 77 155 249 124 62 24 -- -- -- -- n 8 N n 10 N n 16 N n 20 N n 25 N Rev. 3.00 Mar 17, 2006 page 685 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency (MHz) Bit Rate (bit/s) n 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 3 3 2 2 1 1 0 0 0 0 -- 233 116 187 93 187 74 149 74 29 14 -- 2 -- 3 2 2 1 1 0 0 0 -- -- -- -- 128 205 102 205 82 164 82 32 -- -- -- -- 30 N n 33 N 2.5 M 0 5M -- Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 2 4 6 8 10 12 14 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 (MHz) 16 18 20 25 30 33 External Input Clock (MHz) 2.6667 3.0000 3.3333 4.1667 5.0000 5.5000 Maximum Bit Rate (bit/s) 2666666.7 3000000.0 3333333.3 4166666.7 5000000.0 5500000.0 Rev. 3.00 Mar 17, 2006 page 686 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency (MHz) 7.1424 Bit Rate (bit/s) 9600 n 1 N 1 Error (%) 0.00 n 0 10.00 N 1 Error (%) 30 n 0 10.7136 N 1 Error (%) 25 n 0 13.00 N 1 Error (%) 8.99 Operating Frequency (MHz) 14.2848 Bit Rate (bit/s) 9600 n 0 N 1 Error (%) 0.00 n 0 16.00 N 1 Error (%) 12.01 n 0 18.00 N 2 Error (%) 15.99 n 0 20.00 N 2 Error (%) 6.60 Operating Frequency (MHz) 25.00 Bit Rate (bit/s) 9600 n 0 N 3 Error (%) 12.49 n 0 30.00 N 3 Error (%) 5.01 n 0 33.00 N 4 Error (%) 7.59 Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 n 0 0 0 0 0 0 N 0 0 0 0 0 0 (MHz) 18.00 20.00 25.00 30.00 33.00 Maximum Bit Rate (bit/s) 24194 26882 33602 40323 44355 n 0 0 0 0 0 N 0 0 0 0 0 Rev. 3.00 Mar 17, 2006 page 687 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output. 0: Pins TxD0/IrTxD and RxD0/IrRxD function as TxD0 and RxD0 1: Pins TxD0/IrTxD and RxD0/IrRxD function as IrTxD and IrRxD 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 Specifies the high pulse width in IrTxD output pulse encoding when the IrDA function is enabled. 000: Pulse width = B x 3/16 (3/16 of bit rate) 001: Pulse width = /2 010: Pulse width = /4 011: Pulse width = /8 100: Pulse width = /16 101: Pulse width = /32 110: Pulse width = /64 111: Pulse width = /128 3 to 0 -- All 0 -- Reserved These bits are always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 688 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. SEMR is supported only in SCI_2 of the H8S/2678R Group. Bit 7 to 4 Bit Name -- Initial Value Undefined R/W -- Description Reserved If these bits are read, an undefined value will be returned and cannot be modified. ABCS 0 R/W Asynchronous basic clock selection (valid only in asynchronous mode) Selects the basic clock for 1-bit period in asynchronous mode. 0: Operates on a basic clock with a frequency of 16 times the transfer rate. 1: Operates on a basic clock with a frequency of 8 times the transfer rate. 3 Rev. 3.00 Mar 17, 2006 page 689 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Bit 2 1 0 Bit Name ACS2 ACS1 ACS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Asynchronous clock source selection (valid when CKS1 = 1 in asynchronous mode) Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.152 kbps which is the average transfer rate dedicated for = 10.667 MHz. (Operates on a basic clock with a frequency of 16 times the transfer rate.) 010: Selects 460.606 kbps which is the average transfer rate dedicated for = 10.667 MHz. (Operates on a basic clock with a frequency of 8 times the transfer rate.) 011: Selects 720 kbps which is the average transfer rate dedicated for = 32 MHz. (Operates on a basic clock with a frequency of 16 times the transfer rate.) 100: Reserved 101: Selects 115.196 kbps which is the average transfer rate dedicated for = 16 MHz (Operates on a basic clock with a frequency of 16 times the transfer rate.) 110: Selects 460.784 kbps which is the average transfer rate dedicated for = 16 MHz (Operates on a basic clock with a frequency of 16 times the transfer rate.) 111: Selects 720 kbps which is the average transfer rate dedicated for = 16 MHz (Operates on a basic clock with a frequency of 8 times the transfer rate.) Note that the average transfer rate does not correspond to the frequency other than 10.667, 16, or 32 MHz. Rev. 3.00 Mar 17, 2006 page 690 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a doublebuffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 1 1 1 Transmit/receive data 7 or 8 bits Parity Stop bit(s) bit 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 15.4.1 Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 15.5, Multiprocessor Communication Function. Rev. 3.00 Mar 17, 2006 page 691 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit Rev. 3.00 Mar 17, 2006 page 692 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception margin in asynchronous mode is given by formula (1) below. M = (0.5 - { D - 0.5 1 ) - (L - 0.5) F - (1 + F) N 2N } x 100 [%] ... Formula (1) Where M: Reception Margin N: Ratio of bit rate to clock (N = 16) D: Clock duty cycle (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal base clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 3.00 Mar 17, 2006 page 693 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Rev. 3.00 Mar 17, 2006 page 694 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start of initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 15.5 Sample SCI Initialization Flowchart Rev. 3.00 Mar 17, 2006 page 695 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Mar 17, 2006 page 696 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-dataempty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 15.7 Sample Serial Transmission Flowchart Rev. 3.00 Mar 17, 2006 page 697 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Mar 17, 2006 page 698 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains its state before data reception. Rev. 3.00 Mar 17, 2006 page 699 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER FER ORER = 1? ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error handling be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by an RXI interrupt and the RDR value is read. Figure 15.9 Sample Serial Reception Data Flowchart (1) Rev. 3.00 Mar 17, 2006 page 700 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2) Rev. 3.00 Mar 17, 2006 page 701 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle to the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends communication data with a 1 multiprocessor bit added to the ID code of the receiving station. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 3.00 Mar 17, 2006 page 702 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB= 1) ID transmission cycle = receiving station specification H'AA (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 3.00 Mar 17, 2006 page 703 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 3.00 Mar 17, 2006 page 704 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception. Rev. 3.00 Mar 17, 2006 page 705 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 1 Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 ID2 Data2 MPIE bit set to 1 again MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine (b) Data matches station's ID Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 3.00 Mar 17, 2006 page 706 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER ORER = 1? No Read RDRF flag in SSR Yes [4] No RDRF = 1? Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error handling (Continued on next page) Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 3.00 Mar 17, 2006 page 707 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Mar 17, 2006 page 708 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care * MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Bit 0 Note: * High except in continuous transfer Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) 15.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 3.00 Mar 17, 2006 page 709 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Start of initialization Clear TE and RE bits in SCR to 0 Set data transfer format in SMR and SCMR [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE and RE bits in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enable the TxD and RxD pins to be used. [2] Set value in BRR Wait [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 15.15 Sample SCI Initialization Flowchart Rev. 3.00 Mar 17, 2006 page 710 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev. 3.00 Mar 17, 2006 page 711 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine 1 frame TEI interrupt request generated Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 3.00 Mar 17, 2006 page 712 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-dataempty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes Clear TE bit in SCR to 0 Figure 15.17 Sample Serial Transmission Flowchart Rev. 3.00 Mar 17, 2006 page 713 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 15.18 Example of SCI Operation in Reception Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception. Rev. 3.00 Mar 17, 2006 page 714 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1? No [2] [3] Error processing (Continued below) [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by a receivedata-full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Error handling Overrun error handling Clear ORER flag in SSR to 0 Figure 15.19 Sample Serial Reception Flowchart Rev. 3.00 Mar 17, 2006 page 715 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 3.00 Mar 17, 2006 page 716 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Initialization Start of transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read ORER flag in SSR Yes [3] Error handling ORER = 1? No If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit-dataempty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 3.00 Mar 17, 2006 page 717 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.21 shows an example of connection with the Smart Card. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the SCI is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal. VCC TxD RxD SCK Rx (port) This LSI Connected equipment Data line Clock line Reset line I/O CLK RST IC card Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections Rev. 3.00 Mar 17, 2006 page 718 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.2 Data Format (Except for Block Transfer Mode) Figure 15.22 shows the transfer data format in Smart Card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after the elapse of 2 etu or longer. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Legend: : Start bit Ds D0 to D7 : Data bits : Parity bit Dp : Error signal DE Figure 15.22 Normal Smart Card Interface Data Format Data transfer with the types of IC cards (direct convention and inverse convention) are performed as described in the following. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) E Rev. 3.00 Mar 17, 2006 page 719 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) E With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 15.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in normal Smart Card interface, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. 15.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the Rev. 3.00 Mar 17, 2006 page 720 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = (0.5 - 1 D - 0.5 ) - (L - 0.5) F - (1 + F) x 100 [%] 2N N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866% 372 clocks 186 clocks 0 Internal basic clock 185 371 0 185 371 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate) Rev. 3.00 Mar 17, 2006 page 721 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode, after checking that the SCI has finished transmission, initialize the SCI, and clear TE to 0 and set RE to 1. Whether SCI has finished transmission can be checked with the TEND flag. Rev. 3.00 Mar 17, 2006 page 722 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sampled from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Figure 15.28 shows a flowchart for transmission. The sequence of transmit operations can be performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt source. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). Rev. 3.00 Mar 17, 2006 page 723 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 Transfer to TSR from TDR Transfer to TSR from TDR [9] FER/ERS [6] [8] Figure 15.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag generation timing is shown in figure 15.27. I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu 11.0etu When GM = 1 Legend: Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal Figure 15.27 TEND Flag Generation Timing in Transmission Operation Rev. 3.00 Mar 17, 2006 page 724 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.28 Example of Transmission Processing Flow Rev. 3.00 Mar 17, 2006 page 725 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. The receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is generated. Figure 15.30 shows a flowchart for reception. The sequence of receive operations can be performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated, and so the error flag must be cleared to 0. In the event of an error, the DTC or DMAC is not activated and receive data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, refer to section 15.4, Operation in Asynchronous Mode. Transfer frame n+1 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 [2] PER [4] [1] [3] Figure 15.29 Retransfer Operation in SCI Receive Mode Rev. 3.00 Mar 17, 2006 page 726 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.30 Example of Reception Processing Flow 15.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Rev. 3.00 Mar 17, 2006 page 727 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) CKE0 SCK Specified pulse width Specified pulse width Figure 15.31 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure the clock duty cycle from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When changing from smart card interface mode to software standby mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. 4. Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty cycle preserved. 5. Make the transition to the software standby state. Rev. 3.00 Mar 17, 2006 page 728 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) When returning to smart card interface mode from software standby mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty cycle. Normal operation Software standby Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 15.32 Clock Halt and Restart Procedure 15.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600 bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this LSI does not include a function for varying the transfer rate automatically, the transfer rate setting must be changed by software. Figure 15.33 shows a block diagram of the IrDA function. Rev. 3.00 Mar 17, 2006 page 729 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) IrDA SCI0 TxD0/IrTxD Pulse encoder TxD RxD RxD0/IrRxD Pulse decoder IrCR Figure 15.33 Block Diagram of IrDA Transmission: In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.34). When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in IrCR. In the specification, the high pulse width is fixed at a minimum of 1.41 s, and a maximum of (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s. When system clock is 20 MHz, 1.6 s can be set for a high pulse width with a minimum value of 1.41 s. When the serial data is 1, no pulse is output. Rev. 3.00 Mar 17, 2006 page 730 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmit Receive IR frame Start bit 0 1 0 1 0 Data Stop bit 0 1 1 0 1 Bit cycle Pulse width 1.6 s to 3/16 bit cycle Figure 15.34 IrDA Transmit/Receive Operations Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 s will be identified as a 0 signal. High Pulse Width Selection: Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Rev. 3.00 Mar 17, 2006 page 731 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.12 Settings of Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Above) /Bit Period x 3/16 (s) (Below) Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 25 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 57600 3.26 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 115200 1.63 -- -- -- -- 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 110 Legend: --: A bit rate setting cannot be made on the SCI side. Rev. 3.00 Mar 17, 2006 page 732 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.9 15.9.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC or DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Rev. 3.00 Mar 17, 2006 page 733 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.13 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible DMAC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Not possible Not possible Not possible Low Priority High 15.9.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 15.14 SCI Interrupt Sources Channel 0 Name ERI0 RXI0 TXI0 1 ERI1 RXI1 TXI1 2 ERI2 RXI2 TXI2 Interrupt Source Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Receive Error, detection Receive Data Full Transmit Data Empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible DMAC Activation Not possible Possible Possible Not possible Possible Possible Not possible Not possible Not possible Low Priority High Rev. 3.00 Mar 17, 2006 page 734 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) In Smart Card interface mode, as in normal serial communication interface mode, transfer can be carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 15.10 Usage Notes 15.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 15.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Rev. 3.00 Mar 17, 2006 page 735 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) 15.10.3 Mark State and Break Sending When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set PCR to 1 and clear PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 15.10.5 Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. 15.10.6 Restrictions on Use of DMAC or DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 clocks after TDR is updated. (Figure 15.35) * When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI). Rev. 3.00 Mar 17, 2006 page 736 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 clocks. Figure 15.35 Example of Synchronous Transmission Using DTC 15.10.7 Operation in Case of Mode Transition * Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read TDR write TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states during mode transition are shown in figures 15.37 and 15.38. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. * Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made during reception, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Rev. 3.00 Mar 17, 2006 page 737 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.39 shows a sample flowchart for mode transition during reception. All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 No [1] Data being transmitted is interrupted. After exiting software standby mode, normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode. [2] Transition to software standby mode Exit from software standby mode Change operating mode? Yes Initialization [3] No TE = 1 Figure 15.36 Sample Flowchart for Mode Transition during Transmission Rev. 3.00 Mar 17, 2006 page 738 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 15.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 15.38 Port Pin States during Mode Transition (Internal Clock, Synchronous Transmission) Rev. 3.00 Mar 17, 2006 page 739 of 926 REJ09B0283-0300 Section 15 Serial Communication Interface (SCI, IrDA) RDRF = 1 Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? Yes Initialization [2] [2] Includes module stop mode. No RE = 1 Figure 15.39 Sample Flowchart for Mode Transition during Reception Rev. 3.00 Mar 17, 2006 page 740 of 926 REJ09B0283-0300 Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to twelve analog input channels to be selected. The block diagram of A/D converter is shown in figure 16.1. 16.1 Features * 10-bit resolution * Twelve input channels * Conversion time: 6.7 s per channel (at 20-MHz operation) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels (H8S/2678R Group) * Four data registers (H8S/2678 Group) or eight data registers (H8S/2678R Group) Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Conversion can be started by software, 16-bit timer pulse unit (TPU), conversion start trigger by 8-bit timer (TMR), or external trigger signal. * Interrupt request A/D conversion end interrupt (ADI) request can be generated * Module stop mode can be set ADCMS01A_010020020400 Rev. 3.00 Mar 17, 2006 page 741 of 926 REJ09B0283-0300 Section 16 A/D Converter Module data bus Internal data bus AVCC Vref AVSS Successive approximations register 10-bit D/A A D D R A A D D R B A D D R C A D D R D A D D R E * A D D R F * A D D R G * A D D R H * A D C S R A D C R AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN12 AN13 AN14 AN15 + - Multiplexer Comparator Control circuit Sample-andhold circuit Bus interface ADI interrupt signal ADTRG Conversion start trigger from 8-bit timer or TPU A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C ADDRD: ADDRE: ADDRF: ADDRG: ADDRH: A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: Note: * Only in H8S/2678R Group. Figure 16.1 Block Diagram of A/D Converter Rev. 3.00 Mar 17, 2006 page 742 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the A/D converter. The twelve analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN12 to AN15). In the H8S/2678 Group, each channel set is divided into four channels x two groups: group 0 in channel set 0 (AN0 to AN3), group 1 in channel set 0 (AN4 to AN7), and group1 in channel set 1 (AN12 to AN15). The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. Table 16.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN12 AN13 AN14 AN15 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Channel set 1 analog inputs Function Analog block power supply Analog block ground A/D conversion reference voltage Channel set 0 analog inputs Rev. 3.00 Mar 17, 2006 page 743 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.3 Register Descriptions The A/D converter has the following registers. * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D data register E (ADDRE) * A/D data register F (ADDRF) * A/D data register G (ADDRG) * A/D data register H (ADDRH) * A/D control/status register (ADCSR) * A/D control register (ADCR) 16.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD (H8S/2678 Group) and eight 16-bit read-only ADDR registers, ADDRA to ADDRH (H8S/2678R Group), used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 16.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. In the H8S/2678 Group, the data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read directly from the CPU, but the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the only upper byte, or read in word unit. In the H8S/2678R Group, the data bus between the CPU and the A/D converter is 16-bit width. The data can be read directly from the CPU. Rev. 3.00 Mar 17, 2006 page 744 of 926 REJ09B0283-0300 Section 16 A/D Converter Table 16.2 Analog Input Channels and Corresponding ADDR Registers * H8S/2678 Group Analog Input Channel Channel Set 0 (CH3 = 1) Group 0 (CH2 = 0) AN0 AN1 AN2 AN3 Group 1 (CH2 = 1) AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 0) Group 0 (CH2 = 0) Setting prohibited Setting prohibited Setting prohibited Setting prohibited Group 1 (CH2 = 1) AN12 AN13 AN14 AN15 A/D Data Register which stores conversion result ADDRA ADDRB ADDRC ADDRD * H8S/2678R Group Analog Input Channel Channel Set 0 (CH3 = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) Nothing Nothing Nothing Nothing AN12 AN13 AN14 AN15 A/D Data Register which stores conversion result ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH Rev. 3.00 Mar 17, 2006 page 745 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. * H8S/2678 Group Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 When the DTC or DMAC is activated by an ADI interrupt and ADDR is read [Clearing conditions] * * 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. When this bit is set to 1 by software, TPU (trigger), TMR (trigger), or the ADTRG pin, A/D conversion starts. This bit remains set to 1 during A/D conversion. In single mode, cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by a reset, or a transition to hardware standby mode or software. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode Rev. 3.00 Mar 17, 2006 page 746 of 926 REJ09B0283-0300 Section 16 A/D Converter Bit 3 Bit Name CKS Initial Value 0 R/W R/W Description Clock Select Used together with the CKS1 bit in ADCR to set the A/D conversion time. When CKS1 = 0 0: 530 states (max) 1: 68 states (max) When CKS = 1 0: 266 states (max) 1: 134 states (max) 2 1 0 CH2 CH1 CH0 0 0 0 R/W R/W R/W Channel Select 2 to 0 These bits are used together with the SCAN bit in ADCSR and the CH3 bit in ADCR to select the analog input channels. When SCAN = 0, CH3 = 0 When SCAN = 1, CH3 = 0 0XXX: Setting prohibited 0XXX: Setting prohibited 100: AN12 101: AN13 110: AN14 111: AN15 100: AN12 101: AN12 and AN13 110: AN12 to AN14 111: AN12 to AN15 When SCAN = 0, When SCAN = 1, CH3 = 1 CH3 = 1 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 Legend: Note: * X: Don't care. Only 0 can be written in bit 7, to clear the flag. 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5 110: AN4 to AN6 111: AN4 to AN7 Rev. 3.00 Mar 17, 2006 page 747 of 926 REJ09B0283-0300 Section 16 A/D Converter * H8S/2678R Group Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 When the DTC or DMAC is activated by an ADI interrupt and ADDR is read [Clearing conditions] * * 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts an A/D conversion. In single mode, cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode. 4 -- 0 -- Reserved This bit is always read as 0 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 748 of 926 REJ09B0283-0300 Section 16 A/D Converter Bit 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Channel select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 Legend: Note: * X: Don't care. Only 0 can be written in bit 7, to clear the flag. 1000: Setting prohibited 1001: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1100: AN12 1101: AN13 1110: AN14 1111: AN15 1000: Setting prohibited 1001: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1100: AN12 1101: AN12 and AN13 1110: AN12 to AN14 1111: AN12 to AN15 1000: Setting prohibited 1001: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited When SCANE = 1 and SCANS = 0 When SCANE = 1 and SCANS = 1 Rev. 3.00 Mar 17, 2006 page 749 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion start by an external trigger input. * H8S/2678 Group Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger (TPU) is enabled 10: A/D conversion start by external trigger (TMR) is enabled 11: A/D conversion start by external trigger pin (ADTRG) is enabled 5, 4 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. 3 CKS1 1 R/W Clock Select 1 Used together with the CKS bit in ADCSR to set the A/D conversion time. See the description of the CKS bit for details. 2 CH3 1 R/W Channel Select 3 Used together with bits CH2 to CH0 in ADCSR to select the analog input channel(s). See the description of bits CH2 to CH0 for details. 1, 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 750 of 926 REJ09B0283-0300 Section 16 A/D Converter * H8S/2678R Group Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger (TPU) is enabled 10: A/D conversion start by external trigger (TMR) is enabled 11: A/D conversion start by external trigger pin (ADTRG) is enabled 5 4 SCANE SCANS 0 0 R/W R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0x: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8. 3 2 CKS1 CKS0 0 0 R/W R/W Clock Select 1 to 0 Sets the A/D conversion time. Only set bits CKS1 and CKS0 while conversion is stopped (ADST = 0). 00: A/D conversion time = 530 states (max) 01: A/D conversion time = 266 states (max) 10: A/D conversion time = 134 states (max) 11: A/D conversion time = 68 states (max) 1, 0 -- All 0 -- Reserved These bits are always read as 0 and cannot be modified. Legend: X: Don't care. Rev. 3.00 Mar 17, 2006 page 751 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters wait state. 16.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels: maximum four channels or maximum eight channels (H8S/2678R Group). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by a software, TPU or external trigger input, A/D conversion starts on the first channel in the group. In the H8S/2678 Group, the A/D conversion starts on AN0 when CH3 and CH2 =10, AN4 when CH3 and CH2 = 11, or AN12 when CH3 and CH2 = 01. In the H8S/2678R Group, the consecutive A/D conversion on maximum four channels (SCANE and SCANS = 10) or on maximum eight channels (SCANE and SCANS = 11) can be selected. When the consecutive A/D conversion is performed on the four channels, the A/D conversion starts on AN0 when CH3 and CH2 =00, AN4 when CH3 and CH2 = 01, or AN12 when CH3 and CH2 = 11. When the consecutive A/D conversion is performed on the eight channels, the A/D conversion starts on AN0 when SH3 and SH2 =00. Rev. 3.00 Mar 17, 2006 page 752 of 926 REJ09B0283-0300 Section 16 A/D Converter 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the corresponding A/D data register to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when A/D conversion start delay time (tD) passes after the ADST bit is set to 1, then starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D conversion time. As indicated in figure 16.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in tables 16.3. In scan mode, the values given in tables 16.3 apply to the first conversion time. The values given in tables 16.4 apply to the second and subsequent conversions. The conversion time must be within the ranges indicated in the descriptions, A/D Conversion Characteristics in section 24, Electrical Characteristics. Therefore the CKS and CKS1 bits (H8S/2678 Group) or CKS1 and CKS0 bits (H8S/2678R Group) must be set to satisfy this condition. Rev. 3.00 Mar 17, 2006 page 753 of 926 REJ09B0283-0300 Section 16 A/D Converter (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time Figure 16.2 A/D Conversion Timing Table 16.3 A/D Conversion Time (Single Mode) * H8S/2678 Group CKS1 = 0 CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min Typ Max 18 -- -- 33 CKS = 1 Min Typ Max 4 -- 67 -- 15 -- 5 -- 68 CKS1 = 1 CKS = 0 Min Typ Max 10 -- -- 63 17 -- 266 CKS = 1 Min Typ Max 6 -- -- 31 9 -- 134 127 -- 530 515 -- 259 -- 131 -- Note: Values in the table are the number of states. Rev. 3.00 Mar 17, 2006 page 754 of 926 REJ09B0283-0300 Section 16 A/D Converter * H8S/2678R Group CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min Typ Max 18 -- -- 33 CKS0 = 1 Min Typ Max 10 -- -- 63 17 -- 266 CKS1 = 1 CKS0 = 0 Min Typ Max 6 -- -- 31 9 -- 134 CKS0 = 1 Min Typ Max 4 -- 67 -- 15 -- 5 -- 68 127 -- 530 515 -- 259 -- 131 -- Note: Values in the table are the number of states. Table 16.4 A/D Conversion Time (Scan Mode) * H8S/2678 Group CKS1 0 CKS 0 1 1 0 1 Conversion Time (State) 512 (Fixed) 64 (Fixed) 256 (Fixed) 128 (Fixed) * H8S/2678R Group CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) Rev. 3.00 Mar 17, 2006 page 755 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 16.3 External Trigger Input Timing 16.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables an ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 16.5 A/D Converter Interrupt Source Name ADI Interrupt Source End of conversion Interrupt Flag ADF DTC Activation Possible DMAC Activation Possible Rev. 3.00 Mar 17, 2006 page 756 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 16.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 16.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 16.5). * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 3.00 Mar 17, 2006 page 757 of 926 REJ09B0283-0300 Section 16 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 16.5 A/D Conversion Accuracy Definitions Rev. 3.00 Mar 17, 2006 page 758 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.7 16.7.1 Usage Notes Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. 16.7.2 Permissible Signal Source Impedance This LSI's analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 16.6). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. This LSI Equivalent circuit of A/D converter Sensor output impedance Up to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF 20 pF 10 k Figure 16.6 Example of Analog Input Circuit Rev. 3.00 Mar 17, 2006 page 759 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 16.7.4 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAn Vref. * Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVcc Vcc and AVss = Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. * Vref setting range The reference voltage at the Vref pin should be set in the range Vref AVcc. 16.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7 and AN12 to AN15), analog reference power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. Rev. 3.00 Mar 17, 2006 page 760 of 926 REJ09B0283-0300 Section 16 A/D Converter 16.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7 and AN12 to AN15) should be connected between AVcc and AVss as shown in figure 16.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN7 and AN12 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7 and AN12 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 F AVSS 100 AN0 to AN7, AN12 to AN15 Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 16.7 Example of Analog Input Protection Circuit Rev. 3.00 Mar 17, 2006 page 761 of 926 REJ09B0283-0300 Section 16 A/D Converter Table 16.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 10 Unit pF k 10 k AN0 to AN7, AN12 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 16.8 Analog Input Pin Equivalent Circuit Rev. 3.00 Mar 17, 2006 page 762 of 926 REJ09B0283-0300 Section 17 D/A Converter Section 17 D/A Converter 17.1 Features D/A converter features are listed below. * 8-bit resolution * Four output channels * Maximum conversion time of 10 s (with 20-pF load) * Output voltage of 0 V to Vref * D/A output hold function in software standby mode * Setting the module stop mode DAC0001A_000020020400 Rev. 3.00 Mar 17, 2006 page 763 of 926 REJ09B0283-0300 Section 17 D/A Converter Module data bus Bus interface DACR01 DACR23 Internal data bus Vref AVCC DADR0 DADR1 DADR2 DA2 DA1 DA0 AVSS 8-bit D/A Control circuit Legend: DADR0: DADR1: DADR2: DADR3: DACR01: DACR23: D/A data register 0 D/A data register 1 D/A data register 2 D/A data register 3 D/A control register 01 D/A control register 23 Figure 17.1 Block Diagram of D/A Converter Rev. 3.00 Mar 17, 2006 page 764 of 926 REJ09B0283-0300 DADR3 DA3 Section 17 D/A Converter 17.2 Input/Output Pins Table 17.1 shows the pin configuration of the D/A converter. Table 17.1 Pin Configuration Pin Name Analog power pin Analog ground pin Reference voltage pin Analog output pin 0 Analog output pin 1 Analog output pin 2 Analog output pin 3 Symbol AVCC AVSS Vref DA0 DA1 DA2 DA3 I/O Input Input Input Output Output Output Output Function Analog power Analog ground Reference voltage of D/A converter Channel 0 analog output Channel 1 analog output Channel 2 analog output Channel 3 analog output 17.3 Register Descriptions The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A data register 2 (DADR2) * D/A data register 3 (DADR3) * D/A control register 01 (DACR01) * D/A control register 23 (DACR23) 17.3.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) DADR0 to DADR3 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR are converted and output to the analog output pins. Rev. 3.00 Mar 17, 2006 page 765 of 926 REJ09B0283-0300 Section 17 D/A Converter 17.3.2 D/A Control Registers 01 and 23 (DACR01, DACR23) DACR01 and DACR23 control the operation of the D/A converter. DACR01 Bit 7 Bit Name DAOE1 Initial Value 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output (DA1) is disabled 1: Channel 1 D/A conversion is enabled; analog output (DA1) is enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output (DA0) is disabled 1: Channel 0 D/A conversion is enabled; analog output (DA0) is enabled 5 DAE 0 R/W D/A Enable Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 0 and 1 D/A conversions are controlled together. Output of conversion results is always controlled independently by the DAOE0 and DAOE1 bits. For details, see table 17.2. 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 766 of 926 REJ09B0283-0300 Section 17 D/A Converter Table 17.2 Control of D/A Conversion Bit 5 DAE 0 Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 1 0 1 1 0 0 1 1 0 1 Description D/A conversion disabled Channel 0 D/A conversion enabled, channel1 D/A conversion disabled Channel 1 D/A conversion enabled, channel0 D/A conversion disabled Channel 0 and 1 D/A conversions enabled D/A conversion disabled Channel 0 and 1 D/A conversions enabled Rev. 3.00 Mar 17, 2006 page 767 of 926 REJ09B0283-0300 Section 17 D/A Converter DACR23 Bit 7 Bit Name DAOE3 Initial Value 0 R/W R/W Description D/A Output Enable 3 Controls D/A conversion and analog output. 0: Analog output (DA3) is disabled 1: Channel 3 D/A conversion is enabled; analog output (DA3) is enabled 6 DAOE2 0 R/W D/A Output Enable 2 Controls D/A conversion and analog output. 0: Analog output (DA2) is disabled 1: Channel 2 D/A conversion is enabled; analog output (DA2) is enabled 5 DAE 0 R/W D/A Enable Used together with the DAOE2 and DAOE3 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 2 and 3 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 2 and 3 D/A conversions are controlled together. Output of conversion results is always controlled independently by the DAOE2 and DAOE3 bits. For details, see table 17.3. 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Rev. 3.00 Mar 17, 2006 page 768 of 926 REJ09B0283-0300 Section 17 D/A Converter Table 17.3 Control of D/A Conversion Bit 5 DAE 0 Bit 7 DAOE3 0 Bit 6 DAOE2 0 1 1 0 1 1 0 0 1 1 0 1 Description D/A conversion disabled Channel 2 D/A conversion enabled, channel3 D/A conversion disabled Channel 3 D/A conversion enabled, channel2 D/A conversion disabled Channel 2 and 3 D/A conversions enabled D/A conversion disabled Channel 2 and 3 D/A conversions enabled 17.4 Operation The D/A converter includes D/A conversion circuits for four channels, each of which can operate independently. When DAOE bit in DACR01 or DACR23 is set to 1, D/A conversion is enabled and the conversion result is output. The operation example concerns D/A conversion on channel 0. Figure 17.2 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started. The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result is continued to output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The output value is expressed by the following formula: DADR contents x Vref 256 [3] If DADR0 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. [4] If the DAOE0 bit is cleared to 0, analog output is disabled. Rev. 3.00 Mar 17, 2006 page 769 of 926 REJ09B0283-0300 Section 17 D/A Converter DADR0 write cycle DACR01 write cycle DADR0 write cycle DACR01 write cycle Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Legend: tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 17.2 Example of D/A Converter Operation 17.5 17.5.1 Usage Notes Setting for Module Stop Mode It is possible to enable/disable the D/A converter operation using the module stop control register, the D/A converter does not operate by the initial value of the register. The register can be accessed by releasing the module stop mode. For details, see section 22, Power-Down Modes. 17.5.2 D/A Output Hold Function in Software Standby Mode If D/A conversion is enabled and this LSI enters software standby mode, D/A output is held and analog power supply current remains at the same level during D/A conversion. When the analog power supply current is required to go low in software standby mode, bits DAOE0 to DAOE3 and DAE should be cleared to 0, and D/A output should be disabled. Rev. 3.00 Mar 17, 2006 page 770 of 926 REJ09B0283-0300 Section 18 RAM Section 18 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). Product Type Name H8S/2678 Group HD64F2676 HD6432676 HD6432675 HD6432673 HD6412670 H8S/2678R Group HD6412674R ROMless version ROMless version ROM Type Flash memory version Masked ROM version RAM Capacitance 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 32 kbytes RAM Address H'FFA000 to H'FFBFFF H'FFA000 to H'FFBFFF H'FFA000 to H'FFBFFF H'FFA000 to H'FFBFFF H'FFA000 to H'FFBFFF H'FF4000 to H'FFBFFF Rev. 3.00 Mar 17, 2006 page 771 of 926 REJ09B0283-0300 Section 18 RAM Rev. 3.00 Mar 17, 2006 page 772 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Section 19 Flash Memory (F-ZTAT Version) The features of the flash memory included in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.1 * Size Features ROM Size 256 kbytes ROM Address H'000000 to H'03FFFF (Modes 3, 4, 7, 10, and 11) H'100000 to H'13FFFF (Modes 5, 6, 13, and 14) Product Classification H8S/2678 Group HD64F2676 * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory of 384 kbytes is configured as follows: 64 kbytes x 5 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. The 256-kbyte flash memory is configured as follows: 64 kbytes x 3 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Two on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode in which the on-chip boot program is started for erase or programming of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment With data transfer in boot mode, the bit rate of this LSI can be automatically adjusted to match the transfer bit rate of the host. * Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. ROMF251A_000020020400 Rev. 3.00 Mar 17, 2006 page 773 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) * Programming/erasing protection There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase operations. Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR Bus interface/controller Operating mode FWE pin* Mode pins Flash memory Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register Note: * Only in H8S/2678 Group. Figure 19.1 Block Diagram of Flash Memory 19.2 Mode Transitions When the mode pins and the FWE pin* are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. Rev. 3.00 Mar 17, 2006 page 774 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) The differences between boot mode and user program mode are shown in table 19.1. Figure 19.3 shows boot mode. Figure 19.4 shows user program mode. Note: * Only in the H8S/2678 Group. MD1 = 1, MD2 = 0, FWE = 1*1 MD0 = 1, MD1 = 1, MD2 = 0*2 RES = 0 User mode (on-chip ROM enabled) 1 0* E= , FW =1 MD2 = 1*2 D2 M =0 RES Reset state RES = 0 FWE = 1, MD2 = 1, SWE = 1*1 SWE = 1*2 FWE = 0, MD2 = 1, SWE = 0*1 SWE = 0*2 ES = 0 MD0 = 0, MD1 = 0, MD2 = 0, P50 = 0, P51 = 0, P52 = 1 R Programmer mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. Only in H8S/2678 Group. 2. Only in H8S/2678R Group. Figure 19.2 Flash Memory State Transitions Table 19.1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Note: * Yes No User Program Mode Yes Yes Program/program-verify Erase/erase-verify/program/ program-verify emulation To be provided by the user, in accordance with the recommended algorithm. Rev. 3.00 Mar 17, 2006 page 775 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program This LSI Boot program Flash memory RAM SCI This LSI Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program This LSI Boot program Flash memory RAM Boot program area Flash memory prewrite-erase Programming control program This LSI SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Figure 19.3 Boot Mode Rev. 3.00 Mar 17, 2006 page 776 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 1. Initial state (1) The FWE assessment program that confirms that user program mode is entered, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host New application program This LSI Boot program Flash memory FWE assessment program This LSI SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program This LSI Boot program Flash memory FWE assessment program This LSI SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Note: The FWE assessment program is not available in the H8S/2678R Group. Figure 19.4 User Program Mode Rev. 3.00 Mar 17, 2006 page 777 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.3 Block Configuration Figure 19.5 shows the block configuration of 384-kbyte flash memory and figure 19.6 shows that of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384-kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). The 256-kbyte flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower eight bits are H'00 or H'80. Rev. 3.00 Mar 17, 2006 page 778 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) EB0 Erase unit 4 kbytes EB1 Erase unit 4 kbytes EB2 Erase unit 4 kbytes EB3 Erase unit 4 kbytes EB4 Erase unit 4 kbytes EB7 Erase unit 4 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 64 kbytes EB10 Erase unit 64 kbytes EB11 Erase unit 64 kbytes EB12 Erase unit 64 kbytes EB13 Erase unit 64 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F H'000FFF H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00107F H'001FFF H'002000 H'002001 H'002002 Programming unit: 128 bytes H'00207F H'002FFF H'003000 H'003001 H'003002 Programming unit: 128 bytes H'00307F H'003FFF H'004000 H'004001 H'004002 Programming unit: 128 bytes H'00407F H'007000 H'007001 H'007002 Programming unit: 128 bytes H'00707F H'007FFF H'008000 H'008001 H'008002 Programming unit: 128 bytes H'00807F H'00FFFF H'010000 H'010001 H'010002 Programming unit: 128 bytes H'01007F H'01FFFF H'020000 H'020001 H'020002 Programming unit: 128 bytes H'02007F H'02FFFF H'030000 H'030001 H'030002 Programming unit: 128 bytes H'03007F H'03FFFF H'040000 H'040001 H'040002 Programming unit: 128 bytes H'04007F H'04FFFF H'050000 H'050001 H'050002 Programming unit: 128 bytes H'05007F H'05FFFF Note: Addresses H'100000 to H'15FFFF are allocated in modes 5 and 6. Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) Rev. 3.00 Mar 17, 2006 page 779 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) EB0 Erase unit 4 kbytes EB1 Erase unit 4 kbytes EB2 Erase unit 4 kbytes EB3 Erase unit 4 kbytes EB4 Erase unit 4 kbytes EB7 Erase unit 4 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 64 kbytes EB10 Erase unit 64 kbytes EB11 Erase unit 64 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F H'000FFF H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00107F H'001FFF H'002000 H'002001 H'002002 Programming unit: 128 bytes H'00207F H'002FFF H'003000 H'003001 H'003002 Programming unit: 128 bytes H'00307F H'003FFF H'004000 H'004001 H'004002 Programming unit: 128 bytes H'00407F H'007000 H'007001 H'007002 Programming unit: 128 bytes H'00707F H'007FFF H'008000 H'008001 H'008002 Programming unit: 128 bytes H'00807F H'00FFFF H'010000 H'010001 H'010002 Programming unit: 128 bytes H'01007F H'01FFFF H'020000 H'020001 H'020002 Programming unit: 128 bytes H'02007F H'02FFFF H'030000 H'030001 H'030002 Programming unit: 128 bytes H'03007F H'03FFFF Note: Addresses H'100000 to H'13FFFF are allocated in modes 5, 6, 13, and 14. Figure 19.6 256-kbyte Flash Memory Block Configuration (Modes 4, 7, 10, and 11) Rev. 3.00 Mar 17, 2006 page 780 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.4 Input/Output Pins Table 19.2 shows the pin configuration of the flash memory. Table 19.2 Pin Configuration Pin Name RES FWE* MD2 MD1 MD0 P52 P51 P50 TxD1 RxD1 Note: * I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Sets operating mode in programmer mode Sets operating mode in programmer mode Sets operating mode in programmer mode Serial transmit data output Serial receive data input Only in H8S/2678 Group. 19.5 Register Descriptions The flash memory has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * Erase block register 2 (EBR2) * RAM emulation register (RAMER) 19.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8, Flash Memory Programming/Erasing. Rev. 3.00 Mar 17, 2006 page 781 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Bit 7 Bit Name FWE Initial Value 0/1 R/W R Description Flash Write Enable Reflects the input level at the FWE pin. It is set to 1 when a high level is input to the FWE pin, and cleared to 0 when a low level is input. When this bit is cleared to 0, the flash memory transits to the hardware protection state. Note: In the H8S/2678R Group, this bit is reserved. This bit is always read as 0 in modes 1 and 2. This bit is always read as 1 in modes 3 to 7. The initial value should not be changed. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 and EBR2 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1 while FWE = 1* and SWE = 1, the flash memory transits to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. 4 PSU 0 R/W Program Setup When this bit is set to 1 while FWE = 1* and SWE = 1, the flash memory transits to the program setup state. When it is cleared to 0, the program setup state is cancelled. 3 EV 0 R/W Erase-Verify When this bit is set to 1 while FWE = 1* and SWE = 1, the flash memory transits to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1 while FWE = 1* and SWE = 1, the flash memory transits to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. Rev. 3.00 Mar 17, 2006 page 782 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Bit 1 Bit Name E Initial Value 0 R/W R/W Description Erase When this bit is set to 1 while FWE = 1*, SWE = 1, and ESU = 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while FWE = 1*, SWE = 1, and PSU = 1, the flash memory transits to program mode. When it is cleared to 0, program mode is cancelled. Note: * Only in H8S/2678 Group. 19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. When the on-chip flash memory is disabled, the contents of FLMCR2 are always read as H'00. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See 19.9.3 Error Protection, for details. 6 to 0 -- All 0 R Reserved These bits always read as 0. Rev. 3.00 Mar 17, 2006 page 783 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For details, see table 19.3, Erase Blocks. Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 4 kbytes of EB7 are to be erased. When this bit is set to 1, 4 kbytes of EB6 are to be erased. When this bit is set to 1, 4 kbytes of EB5 are to be erased. When this bit is set to 1, 4 kbytes of EB4 are to be erased. When this bit is set to 1, 4 kbytes of EB3 is to be erased. When this bit is set to 1, 4 kbytes of EB2 is to be erased. When this bit is set to 1, 4 kbytes of EB1 is to be erased. When this bit is set to 1, 4 kbytes of EB0 is to be erased. Rev. 3.00 Mar 17, 2006 page 784 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR2 and EBR1 together (do not set more than one bit at the same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For details, see table 19.3, Erase Blocks. Bit 7, 6 5 Bit Name -- EB13 Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. When this bit is set to 1, 64 kbytes of EB13 are to be erased. Note: In the H8S/2678 Group, this bit is reserved. The initial value should not be changed. 4 EB12 0 R/W When this bit is set to 1, 64 kbytes of EB12 are to be erased. Note: In the H8S/2678 Group, this bit is reserved. The initial value should not be changed. 3 2 1 0 EB11 EB10 EB9 EB8 0 0 0 0 R/W R/W R/W R/W When this bit is set to 1, 64 kbytes of EB11 are to be erased. When this bit is set to 1, 64 kbytes of EB10 are to be erased. When this bit is set to 1, 64 kbytes of EB9 are to be erased. When this bit is set to 1, 32 kbytes of EB8 are to be erased. Rev. 3.00 Mar 17, 2006 page 785 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Table 19.3 Erase Blocks Address Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) EB12 (64 kbytes) EB13 (64 kbytes) H8S/2678R Group: Modes 3, 4, and 7 H8S/2678 Group: Modes 4, 7, 10, and 11 H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF H'040000 to H'04FFFF H'050000 to H'05FFFF H8S/2678R Group: Modes 5 and 6 H8S/2678 Group: Modes 5, 6, 13, and 14 H'100000 to H'100FFF H'101000 to H'101FFF H'102000 to H'102FFF H'103000 to H'103FFF H'104000 to H'104FFF H'105000 to H'105FFF H'106000 to H'106FFF H'107000 to H'107FFF H'108000 to H'10FFFF H'110000 to H'11FFFF H'120000 to H'12FFFF H'130000 to H'13FFFF H'140000 to H'14FFFF H'150000 to H'15FFFF Note: The erase blocks of the 384-kbyte flash memory are EB0 to EB13. The erase blocks of the 256-kbyte flash memory are EB0 to EB11. 19.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Rev. 3.00 Mar 17, 2006 page 786 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Bit 7, 5 4 3 Bit Name -- -- RAMS Initial Value All 0 0 0 R/W R R/W R/W Description Reserved These bits always read as 0. Reserved The initial value should not be changed. RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are in the program/eraseprotect state. When this bit is cleared to 0, the RAM emulation function is invalid. 2 1 0 RAM2 RAM1 RAM0 0 0 0 R/W R/W R/W Flash Memory Area Selection When the RAMS bit is set to 1, selects one of the following flash memory areas to overlap the RAM area. The areas correspond with 4-kbyte erase blocks. H8S/2678R Group: Modes 3, 4, and 7 H8S/2678 Group: Modes 4, 7, 10, and 11 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7) H8S/2678R Group: Modes 5 and 6 H8S/2678 Group: Modes 5, 6, 13, and 14 000: H'100000 to H'100FFF (EB0) 001: H'101000 to H'101FFF (EB1) 010: H'102000 to H'102FFF (EB2) 011: H'103000 to H'103FFF (EB3) 100: H'104000 to H'104FFF (EB4) 101: H'105000 to H'105FFF (EB5) 110: H'106000 to H'106FFF (EB6) 111: H'107000 to H'107FFF (EB7) Rev. 3.00 Mar 17, 2006 page 787 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.6 On-Board Programming Modes In an on-board programming mode, programming, erasing, and verification for the on-chip flash memory can be performed. There are two on-board programming modes: boot mode and user program mode. Table 19.4 shows how to select boot mode. User program mode can be selected by setting the control bits by software. For a diagram that shows mode transitions of flash memory, see figure 19.2. Table 19.4 Setting On-Board Programming Modes * H8S/2678 Group Mode Setting Boot mode Expanded mode with on-chip ROM enabled Single-chip activation expanded mode with on-chip ROM enabled User program mode Expanded mode with on-chip ROM enabled External ROM activation expanded 1 mode with on-chip ROM enabled* External ROM activation expanded 2 mode with on-chip ROM enabled* Single-chip activation expanded mode with on-chip ROM enabled FWE 1 1 1 1 1 1 MD2 0 0 1 1 1 1 MD1 1 1 0 0 1 1 MD0 0 1 0 1 0 1 Notes: 1. The initial setting for the external bus width is 16 bits. 2. The initial setting for the external bus width is 8 bits * H8S/2678R Group Mode Setting Boot mode Single-chip activation expanded mode with on-chip ROM enabled MD2 0 MD1 1 MD0 1 Rev. 3.00 Mar 17, 2006 page 788 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.6.1 Boot Mode When this LSI enters boot mode, the embedded boot program is started. The boot program transfers the programming control program from the externally connected host to the on-chip RAM via the SCI_1. When the flash memory is all erased, the programming control program is executed. Table 19.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The transfer format is 8-bit data, 1 stop bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period. 2. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19.6. 3. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 19.8, Flash Memory Programming/Erasing. 4. Before branching to the programming control program, the chip terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of program data or verify data with the host. The TxD pin is high. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 5. In boot mode, if flash memory contains data (all data is not 1), all blocks of flash memory are erased. Boot mode is used for the initial programming in the on-board state or for a forcible Rev. 3.00 Mar 17, 2006 page 789 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) return when a program that is to be initiated in user program mode was accidentally erased and could not be executed in user program mode. Notes: 1. In boot mode, a part of the on-chip RAM area (H'FF8000 to H'FF87FF) is used by the boot program. Addresses H'FF8800 to H'FFBFFF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 2. Boot mode can be cleared by a reset. Release the reset by setting the MD pins, after waiting at least 20 states since driving the reset pin low. Boot mode is also cleared when the WDT overflow reset occurs. 3. Do not change the MD pin input levels in boot mode. 4. All interrupts are disabled during programming or erasing of the flash memory. Rev. 3.00 Mar 17, 2006 page 790 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Table 19.5 Boot Mode Operation Item Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot mode initiation Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 Transmits data H'55 when data H'00 is received error-free. H'00 H'55 H'AA * Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI_1. * Transmits data H'00 to host as adjustment end indication. Transmits data H'AA to host when data H'55 is received. H'AA reception Transfer of number of bytes of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Upper bytes, lower bytes Echoback Echobacks the 2-byte data received to host. Transmits 1-byte of programming control program (repeated for N times) H'XX Echoback Echobacks received data to host and also transfers it to RAM. (repeated for N times) Flash memory erase Boot program erase error H'FF H'AA reception. H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 3.00 Mar 17, 2006 page 791 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 19,200 bps 9,600 bps System Clock Frequency Range of LSI 8 to 25 MHz 8 to 25 MHz 19.6.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the program/erase program or a program which provides the program/erase program from external memory. Because the flash memory itself cannot be read during programming/erasing, transfer the program/erase program to on-chip RAM, as like in boot mode. Figure 19.7 shows a sample procedure for programming/erasing in user program mode. Prepare a program/erase program in accordance with the description in section 19.8, Flash Memory Programming/Erasing. Rev. 3.00 Mar 17, 2006 page 792 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM FWE = high* Execute user program/erase control program (flash memory programming) Clear FWE* Branch to flash memory application program Note: * Not available in H8S/2678R Group. Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode 19.7 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables RAM to be overlapped onto the part of flash memory area so that data to be programmed to flash memory can be emulated in the on-chip RAM in real time. Emulation can be performed in user mode or user program mode. Figure 19.8 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. Rev. 3.00 Mar 17, 2006 page 793 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.8 Flowchart for Flash Memory Emulation in RAM Example in which flash memory block is overlapped is shown in figure 19.9. 1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range of H'FFA000 to H'FFAFFF. 2. The flash memory area to overlap is selected by RAMER from a 4-kbyte area among one of the EB0 to EB7 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. Notes: 1. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. Rev. 3.00 Mar 17, 2006 page 794 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFA000 Flash memory EB8 to EB13 On-chip RAM H'FFBFFF H'5FFFF 384-kbyte flash memory H'FFAFFF Figure 19.9 Example of RAM Overlap Operation 19.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode. The programming control program in boot mode and the user program/erase program in user mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 19.8.1, Program/Program-Verify, and section 19.8.2, Erase/Erase-Verify, respectively. Rev. 3.00 Mar 17, 2006 page 795 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.8.1 Program/Program-Verify When programming data or programs to the flash memory, the program/program-verify flowchart shown in figure 19.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be programmed to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 19.10. 4. Consecutively transfer 128 bytes of data in byte units from the programming data area, reprogramming data area, or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 19.10 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (y + z2 + + ) s as the WDT overflow period. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence to the same bit (N) must not be exceeded. Rev. 3.00 Mar 17, 2006 page 796 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Write pulse application subroutine Write pulse application Enable WDT Set PSU bit in FLMCR1 Wait (y) s Set P bit in FLMCR1 *6 Start of programming Start Set SWE bit in FLMCR1 Wait (x) ms Store 128-byte program data in program data area and reprogram data area n=1 *6 *4 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Wait (z1) ms or (z2) ms or (z3) ms Clear P bit in FLMCR1 Wait () ms Clear PSU bit in FLMCR1 Wait () ms Disable WDT End sub *5 *6 m=0 Write 128-byte data in RAM reprogram *1 data area consecutively to flash memory Sub-routine-call *6 Write pulse application (z1) s or (z2) s Set PV bit in FLMCR1 Wait () ms H'FF dummy write to verify address Increment address Wait () ms Read verify data *2 nn+1 *6 See note 7 for pulse width *6 Note 7: Write Pulse Width Write Time (z) ms Number of Writes (n) z1 1 z1 2 z1 3 z1 4 z1 5 z1 6 z2 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 . . . . . . z2 998 z2 999 z2 1000 Write data = verify data? OK 6n? NG m=1 NG OK Additional program data computation Transfer additional program data to additional program data area Reprogram data computation Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait () ms *6 NG *4 Note: Use a z3 s write pulse for additional programming. RAM Program data storage area (128 bytes) NG Reprogram data storage area (128 bytes) *3 *4 Additional program data storage area (128 bytes) 6n? Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. 3. The reprogram data is given by the operation of the following tables (comparison between stored data in the program data area and verify data). Programming is executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for which programming has been completed will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte areas for storing program data, reprogram data, and additional program data must be provided in the RAM. The contents of the reprogram and additional program data are modified as programming proceeds. 5. A write pulse of (z1) or (z2) s should be applied according to the progress of the programming operation. See note 7 for the pulse widths. When writing of additional-programming data is executed, a (z3) s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. For the values of x, y, z1, z2, z3, , , , , , , and N, see section 24.6, Flash Memory Characteristics. Program Data Operation Chart Original Data Verify Data Reprogram Data Comments (D) (V) (X) 1 0 Programming completed 0 0 Programming incomplete; reprogram 1 1 1 0 Still in erased state; no action 1 OK Sequentially write 128-byte data in additional program data area in RAM to *1 flash memory Sub-routine-call Write pulse application (z3) s *6 (additional programming) *6 m = 0? OK Clear SWE bit in FLMCR1 Wait () ms End of programming NG n (N)? OK NG Clear SWE bit in FLMCR1 *6 Wait () ms Programming failure *6 Additional Program Data Operation Chart Reprogram Data Verify Data Additional Program (X') (V) Data (Y) 0 0 0 1 1 1 0 1 Comments Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Figure 19.10 Program/Program-Verify Flowchart Rev. 3.00 Mar 17, 2006 page 797 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (y + z + + ) ms as the WDT overflow period. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence (N) must not be exceeded. 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased, and while the boot program is executing in boot mode. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. If the interrupt exception handling is started when the vector address has not been programmed yet or the flash memory is being programmed or erased, the vector would not be read correctly, possibly resulting in CPU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. Rev. 3.00 Mar 17, 2006 page 798 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Start *1 Set SWE bit in FLMCR1 Wait (x) s n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) s Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait () s Clear ESU bit in FLMCR1 Wait () s Disable WDT Set EV bit in FLMCR1 Wait () s Set block start address to verify address *2 *2 *2 Start of erase *2 Halt erase *2 nn+1 *4 *2 H'FF dummy write to verify address Wait () s Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait () s *2 NG *5 End of erasing of all erase blocks? OK *2 n N? OK Clear SWE bit in FLMCR1 *2 Wait () s Erase failure *2 Clear EV bit in FLMCR1 Wait () s *2 NG *2 *3 NG Clear SWE bit in FLMCR1 Wait () s End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0) is not necessary. The values of x, y, z, , , , , , , and N are shown in section 24.6, Flash Memory Characteristics. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 19.11 Erase/Erase-Verify Flowchart Rev. 3.00 Mar 17, 2006 page 799 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 19.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1 (this operation must be executed in the on-chip RAM or external memory). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1) and erase block register 2 (EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. 19.9.3 Error Protection In error protection, an error is detected when the CPU's runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When flash memory is read during programming/erasing (including a vector read or instruction fetch) * When an exception handling (excluding a reset) is started during programming/erasing * When a SLEEP instruction is executed during programming/erasing * When the CPU releases the bus mastership during programming/erasing Rev. 3.00 Mar 17, 2006 page 800 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. The error protection state can be canceled by a power-on reset or in hardware standby mode. 19.10 Programmer Mode In programmer mode, a PROM programmer can perform programming/erasing via a socket adapter, just like for a discrete flash memory. Use a PROM programmer which supports the Renesas 512-kbyte flash memory on-chip MCU device type (FZTAT512V3A). A 12-MHz input clock is needed. 19.11 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read. * Standby mode All flash memory circuits are halted. Table 19.7 shows the correspondence between the operating modes of this LSI and the flash memory. When the flash memory returns to normal operation from a standby state, a power supply circuit stabilization period is needed. When the flash memory returns to its normal operating state, bits STS3 to STS0 in SBYCR must be set to provide a wait time of at least 100 s, even when the external clock is being used. Table 19.7 Flash Memory Operating States Operating Mode Active mode Sleep mode Standby mode Flash Memory Operating State Normal operating state Normal operating state Standby state Rev. 3.00 Mar 17, 2006 page 801 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.12 Usage Notes Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. 2. Reset the flash memory before turning on/off the power. When applying or disconnecting Vcc power, fix the RES pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. 3. Powering on and off. Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. The power-on and power-off timing in the H8S/2678 Group is shown in figure 19.12. 4. FWE application/disconnection. FWE application should be carried out when this LSI operation is in a stable condition. If this LSI operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE, ESU, PSU, EV, PV, and E bits in FLMCR1 are cleared. Rev. 3.00 Mar 17, 2006 page 802 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 5. Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when programming or erasing flash memory. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 6. Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 7. Do not set or clear the SWE bit during execution of a program in flash memory. Wait for at least 100 s after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten. When the SWE bit is set to 1, data in flash memory can be read only in program-verify/erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. 8. Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled during programming/erasing the flash memory to give priority to program/erase operations. 9. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. 10. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. 11. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. 12. Apply the reset signal after the SWE, bit is cleared during its operation. The reset signal is applied at least 100 s after the SWE bit has been cleared. Rev. 3.00 Mar 17, 2006 page 803 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing Wait time: 100 s possible tOSC1 VCC Min 0 s FWE tMDS*3 Min 0 s MD2 to MD0*1 tMDS*3 RES SWE set SWE bit (1) Boot Mode Programming/ erasing possible Wait time: 100 s SWE cleared Wait time: x tOSC1 VCC Min 0 s FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit (2) User Program Mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 24.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns SWE cleared Figure 19.12 Power-On/Off Timing (H8S/2678 Group) Rev. 3.00 Mar 17, 2006 page 804 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing possible Wait time: 100 s tOSC1 VCC MD2 to MD0*1 tMDS*3 RES SWE set SWE bit (1) Boot Mode Programming/ erasing possible Wait time: 100 s SWE cleared Min 0 s Wait time: x tOSC1 VCC MD2 to MD0*1 tMDS*3 RES SWE set SWE bit (2) User Program Mode Min 0 s SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 24.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.13 Power-On/Off Timing (H8S/2678R Group) Rev. 3.00 Mar 17, 2006 page 805 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/erasing possible Wait time: x Wait time: x Programming/erasing Programming/erasing possible possible Wait time: x Programming/erasing possible tOSC1 VCC Min 0 s FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set Mode change*1 Boot mode SWE cleared Mode User change*1 mode User program mode User mode User program mode SWE bit (1) H8S/2678 Group Wait time: x Wait time: x Programming/erasing Programming/erasing possible possible Wait time: x Programming/erasing possible Wait time: x Programming/erasing possible *4 tOSC1 VCC *4 *4 *2 tMDS MD2 to MD0 tMDS tRESW RES SWE set SWE cleared SWE bit Mode change*1 Boot mode Mode change*1 User mode User User program mode mode User program mode User mode User program mode (2) H8S/2678R Group Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR, LWR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200 ns is necessary with respect to RES clearance timing. 3. See section 24.6, Flash Memory Characteristics. 4. Wait time: 100 s Figure 19.14 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 3.00 Mar 17, 2006 page 806 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) 19.13 Note on Switching from F-ZTAT Version to Masked ROM Version Care is required if application software developed on the F-ZTAT version is used when the FZTAT version is switched to the masked ROM version product. If an address in which a register for the F-ZTAT version is present is read (see section 23.1, Register Addresses (by functional module, in order of the corresponding section numbers)) in the masked ROM version, an undefined value will be returned. If application software developed on the F-ZTAT version is used in the masked ROM version product, the state of the FWE pin cannot be judged. The program must be modified so that the part of reprogramming (erasing/programming) the flash memory and the part of the RAM emulation are not started. Also, the mode pin of boot mode must not be set in the masked ROM version. Note: This note is applied to all products in the F-ZTAT version and in the masked ROM version of same Group with the different ROM size. Rev. 3.00 Mar 17, 2006 page 807 of 926 REJ09B0283-0300 Section 19 Flash Memory (F-ZTAT Version) Rev. 3.00 Mar 17, 2006 page 808 of 926 REJ09B0283-0300 Section 20 Masked ROM Section 20 Masked ROM This Group microcomputer has 64, 128, or 256 kbytes of on-chip masked ROM. The on-chip ROM is connected to the CPU, data transfer controller (DTC), and DMA controller (DMAC) with a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in the on-chip ROM can always be accessed in one state. Internal data bus (upper 8 bits) Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'100000 H'100002 H'100001 H'100003 H'03FFFE Modes 4 and 7 H'03FFFF H'13FFFE Modes 5 and 6 H'13FFFF Figure 20.1 Block Diagram of 256-kbyte Masked ROM (HD6432676) Internal data bus (upper 8 bits) Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'100000 H'100002 H'100001 H'100003 H'01FFFE Modes 4 and 7 H'01FFFF H'11FFFE Modes 5 and 6 H'11FFFF Figure 20.2 Block Diagram of 128-kbyte Masked ROM (HD6432675) Rev. 3.00 Mar 17, 2006 page 809 of 926 REJ09B0283-0300 Section 20 Masked ROM Internal data bus (upper 8 bits) Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'100000 H'100002 H'100001 H'100003 H'00FFFE Modes 4 and 7 H'00FFFF H'10FFFE Modes 5 and 6 H'10FFFF Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673) The operating mode enables or disables the on-chip ROM. The operating mode is selected by the mode setting pins, such as the FWE and MD2 to MD0 pins as shown in table 3.1. Select modes 4 to 7 when the on-chip ROM is used, and mode 1 or 2 when the on-chip ROM is not used. The onchip ROM is allocated in area 0. Rev. 3.00 Mar 17, 2006 page 810 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock () and internal clocks. The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider. Figure 21.1 shows a block diagram of the clock pulse generator. PLLCR STC0, STC1 SCKCR SCK2 to SCK0 EXTAL Oscillator XTAL PLL circuit (x1, 2, 4) Divider Legend: PLLCR: PLL system control register SCKCR: System clock control register System clock to pin Internal clock to peripheral modules Figure 21.1 Block Diagram of Clock Pulse Generator The frequency can be changed by means of the PLL circuit. Frequency changes are made by software by means of settings in the PLL control register (PLLCR) and the system clock control register (SCKCR). 21.1 Register Descriptions The clock pulse generator has the following registers. * System clock control register (SCKCR) * PLL control register (PLLCR) CPG0400A_010020020400 Rev. 3.00 Mar 17, 2006 page 811 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator 21.1.1 System Clock Control Register (SCKCR) SCKCR controls clock output and selects operation when the frequency multiplication factor used by the PLL circuit is changed, and the division ratio used by the divider. Bit 7 Bit Name PSTOP Initial Value 0 R/W R/W Description Clock Output Disable Controls output. Normal Operation 0: output 1: Fixed high Sleep Mode 0: output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance All module clock stop mode 0: output 1: Fixed high 6 -- 0 R/W Reserved This bit can be read from or written to. However, The write value should always be 0. 5, 4 -- All 0 R/W Reserved These bits are always read as 0. However, the write value should always be 0. 3 STCS 0 R/W Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLL circuit frequency multiplication factor is changed. 0: Specified multiplication factor is valid after transition to software standby mode 1: Specified multiplication factor is valid immediately after STC1 and STC0 bits are rewritten Rev. 3.00 Mar 17, 2006 page 812 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator Bit 2 1 0 Bit Name SCK2 SCK1 SCK0 Initial Value 0 0 0 R/W R/W R/W R/W Description System Clock Select 2 to 0 Select the division ratio. 000: 1/1 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 11X: Setting prohibited Legend: X: Don't care 21.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the PLL circuit. Bit 7 to 4 3 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0 and cannot be modified. -- 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 2 -- 0 R/W Reserved This bit is always read as 0 and cannot be modified. 1 0 STC1 STC0 0 0 R/W R/W Frequency Multiplication Factor The STC bits specify the frequency multiplication factor used by the PLL circuit. 00: x 1 01: x 2 10: x 4 11: Setting prohibited Rev. 3.00 Mar 17, 2006 page 813 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator 21.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 21.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 21.2. Select the damping resistance Rd according to table 20.1. An AT-cut parallel-resonance type should be used. Figure 21.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 21.2. When a crystal resonator is used, the range of its frequencies is from 8 to 25 MHz. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 21.2 Connection of Crystal Resonator (Example) Table 21.1 Damping Resistance Value Frequency (MHz) Rd () 8 200 12 0 16 0 20 0 25 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 21.3 Crystal Resonator Equivalent Circuit Rev. 3.00 Mar 17, 2006 page 814 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator Table 21.2 Crystal Resonator Characteristics Frequency (MHz) RS max () C0 max (pF) 8 80 7 12 60 7 16 50 7 20 40 7 25 40 7 21.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 21.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. Table 21.3 shows the input conditions for the external clock. When an external clock is used, the range of its frequencies is from 8 to 25 MHz. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Counter clock input at XTAL pin Figure 21.4 External Clock Input (Examples) Rev. 3.00 Mar 17, 2006 page 815 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator Table 21.3 External Clock Input Conditions VCC = 3.0 V to 3.6 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width Clock high pulse width Symbol tEXL tEXH tEXr tEXf tCL tCH Min 15 15 -- -- 0.4 0.4 Max -- -- 5 5 0.6 0.6 Unit ns ns ns ns tcyc tcyc Test Conditions Figure 21.5 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 21.5 External Clock Input Timing 21.3 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR. The phase of the rising edge of the internal clock is controlled so as to match that of the rising edge of the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0, the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR. For details on SBYCR, refer to section 22.1.1, Standby Control Register (SBYCR). 1. The initial PLL circuit multiplication factor is 1. Rev. 3.00 Mar 17, 2006 page 816 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator 2. A value is set in bits STS3 to STS0 to give the specified transition time. 3. The target value is set in bits STC1 and STC0, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS3 to STS0. 6. After the set transition time has elapsed, this LSI resumes operation using the target multiplication factor. When STCS = 1, this LSI operates using the new multiplication factor immediately after bits STC1 and STC0 are rewritten. 21.4 Frequeny Divider The frequency divider divides the PLL output clock to generate a 1/2, 1/4, 1/8, 1/16, or 1/32 clock. 21.5 21.5.1 Usage Notes Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of changes according to the setting of SCKCR and PLLCR. Select the clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of must be specified from 8 MHz (min) to 33 MHz (max); outside of this range must be prevented. 2. All the on-chip peripheral modules operate on the . Therefore, note that the time processing of modules such as a timer and SCI differ before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software Standby Mode, in section 22.2.3, Software Standby Mode, for details. 3. Note that the frequency of will be changed when setting SCKCR or PLLCR while executing the external bus cycle with the write-data-buffer function or the EXDMAC. 21.5.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the oscillator connection examples shown in this section as a guide. As the parameters for the oscillation circuit will depend on the floating capacitance of the resonator and the user board, the parameters should be determined in Rev. 3.00 Mar 17, 2006 page 817 of 926 REJ09B0283-0300 Section 21 Clock Pulse Generator consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 21.5.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. See figure 21.6. Avoid Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 21.6 Note on Board Design for Oscillation Circuit Figure 21.7 shows the external circuitry recommended for the PLL circuit. Separate PLLVcc and PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. Rp: 200 PLLVCC CPB: 0.1 F* PLLVSS VCC CB: 0.1 F* VSS Note: * CB and CPB are laminated ceramic capacitors. Figure 21.7 Recommended External Circuitry for PLL Circuit Rev. 3.00 Mar 17, 2006 page 818 of 926 REJ09B0283-0300 Section 22 Power-Down Modes Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI's operating modes are high-speed mode and six power down modes: * Clock division mode * Sleep mode * Module stop mode * All module clock stop mode * Software standby mode * Hardware standby mode Sleep mode is a CPU state, clock division mode is a CPU and bus master state, and module stop mode is an on-chip peripheral function (including bus masters other than the CPU) state. A combination of these modes can be set. After a reset, this LSI is in high-speed mode. Table 22.1 shows the internal states of this LSI in each mode. Figure 21.1 shows the mode transition diagram. LPWS261A_010020020400 Rev. 3.00 Mar 17, 2006 page 819 of 926 REJ09B0283-0300 Section 22 Power-Down Modes Table 22.1 Operating Modes High Speed Mode Clock Division Mode Functions Functions Sleep Mode Functions Halted Retained Functions Functions Functions Functions Functions All Module Software Module Clock Stop Standby Stop Mode Mode Mode Functions Functions Functions Halted Halted Halted Retained Functions Hardware Standby Mode Halted Halted Undefined Halted Operating State Clock pulse generator Functions CPU Instruction Functions execution Register External interrupts NMI IRQ0 to 15 Functions Functions Peripheral WDT functions TMR Functions Functions Functions Functions Functions Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Reset) Functions Functions Functions Halted (Retained) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Halted (Reset) Retained High impedance Functions/ Halted Halted (Retained) (Retained)* Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Reset) Functions Retained Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Retained) Halted (Reset) Halted (Reset) Retained Retained EXDMAC Functions DMAC DTC TPU PPG D/A A/D SCI RAM I/O Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Notes: "Halted (Retained)" in the table means that internal register values are retained and internal operations are suspended. "Halted (Reset)" in the table means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * The active or halted state can be selected by means of the MSTP0 bit in MSTPCR. Rev. 3.00 Mar 17, 2006 page 820 of 926 REJ09B0283-0300 Section 22 Power-Down Modes STBY pin = low Reset state Hardware standby mode STBY pin = high RES pin = low RES pin = high SSBY = 0 SLEEP instruction High-speel mode (Internal clock is PLL circuit output clock) Sleep mode MSTPCR = H'FFFF (H'FFFE), SSBY = 0 All module-clocks-stop mode Any interrupt SLEEP instruction Interrupt*1 SLEEP instruction SCK2 to SCK0 = 0 SCK2 to SCK0 0 Clock division mode SSBY = 1 Software standby mode External interrupt*2 Program execution state : Transition after exception handling Program-halted state : Power- down mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state, a transition to hardware standby mode occurs when STBY is driven low. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. 1. NMI, IRQ0 to IRQ15, 8-bit timer interrupts, watchdog timer interrupts. (8-bit timer interrupts are valid when MSTP0 = 0.) 2. NMI, IRQ0 to IRQ15 (IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1.) Figure 22.1 Mode Transitions Rev. 3.00 Mar 17, 2006 page 821 of 926 REJ09B0283-0300 Section 22 Power-Down Modes 22.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). * System clock control register (SCKCR) * Standby control register (SBYCR) * Module stop control register H (MSTPCRH) * Module stop control register L (MSTPCRL) 22.1.1 Standby Control Register (SBYCR) SBYCR performs software standby mode control. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. This bit should be written 0 when clearing. 6 OPE 1 R/W Output Port Enable Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS) is retained or set to the high-impedance state in software standby mode. 0: In software standby mode, address bus and bus control signals are high-impedance 1: In software standby mode, address bus and bus control signals retain output state Rev. 3.00 Mar 17, 2006 page 822 of 926 REJ09B0283-0300 Section 22 Power-Down Modes Bit 5, 4 Bit Name -- Initial Value All 0 R/W -- Description Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 STS3 STS2 STS1 STS0 1 1 1 1 R/W R/W R/W R/W Standby Timer Select 3 to 0 These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 22.2 and make a selection according to the operating frequency so that the standby time is at least the oscillation stabilization time. With an external clock, a PLL circuit stabilization time is necessary. Refer to table 22.2 to set the wait time. When DRAM is used and selfrefreshing in the software standby state is selected, note that the DRAM's tRAS (self-refresh RAS pulse width) specification must be satisfied. With the F-ZTAT version, a flash memory stabilization time must be provided. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: Setting prohibited 0100: Setting prohibited 0101: Standby time = 64 states 0110: Standby time = 512 states 0111: Standby time = 1024 states 1000: Standby time = 2048 states 1001: Standby time = 4096 states 1010: Standby time = 16384 states 1011: Standby time = 32768 states 1100: Standby time = 65536 states 1101: Standby time = 131072 states 1110: Standby time = 262144 states 1111: Standby time = 524288 states Rev. 3.00 Mar 17, 2006 page 823 of 926 REJ09B0283-0300 Section 22 Power-Down Modes 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. MSTPCRH Bit 15 Bit Name ACSE Initial Value 0 R/W R/W Module All-Module-Clocks-Stop Mode Enable Enables or disables all-module-clocks-stop mode, in which, when the CPU executes a SLEEP instruction after module stop mode has been set for all the on-chip peripheral functions controlled by MSTPCR or the on-chip peripheral functions except the TMR. 0: All-module-clocks-stop mode disabled 1: All-module-clocks-stop mode enabled 14 13 12 11 10 9 8 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W EXDMA controller (EXDMAC) DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG) D/A converter (channels 0 and 1) D/A converter (channels 2 and 3) Rev. 3.00 Mar 17, 2006 page 824 of 926 REJ09B0283-0300 Section 22 Power-Down Modes MSTPCRL Bit 7 6 5 4 3 2 1 0 Bit Name MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module -- A/D converter -- -- Serial communication interface 2 (SCI_2) Serial communication interface 1 (SCI_1) Serial communication interface 0 (SCI_0) 8-bit timer (TMR) 22.2 22.2.1 Operation Clock Division Mode When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and on-chip peripheral functions all operate on the operating clock (1/2, 1/4, 1/8, 1/16, or 1/32) specified by bits SCK2 to SCK0. Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode at the end of the bus cycle, and clock division mode is cleared. If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored. If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters software standby mode. When software standby mode is cleared by an external interrupt, clock division mode is restored. When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The same applies to a reset caused by watchdog timer overflow. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 3.00 Mar 17, 2006 page 825 of 926 REJ09B0283-0300 Section 22 Power-Down Modes 22.2.2 Sleep Mode Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. * Exiting Sleep Mode by Interrupts When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. * Exiting Sleep Mode by RES Pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high starts the CPU performing reset exception processing. * Exiting Sleep Mode by STBY Pin When the STBY pin level is driven low, a transition is made to hardware standby mode. 22.2.3 Software Standby Mode Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the highimpedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ15), or by means of the RES pin or STBY pin. Setting the SSI bit in SSIER to 1 enables IRQ0 to IRQ15 to be used as software standby mode clearing sources. * Clearing with an Interrupt When an NMI or IRQ0 to IRQ15 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ15 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to Rev. 3.00 Mar 17, 2006 page 826 of 926 REJ09B0283-0300 Section 22 Power-Down Modes IRQ15 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the RES Pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY Pin When the STBY pin is driven low, a transition is made to hardware standby mode. Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to STS0 in SBYCR should be set as described below. * Using a Crystal Oscillator Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 22.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0. * Using an External Clock A PLL circuit stabilization time is necessary. Refer to table 22.2 to set the wait time. Rev. 3.00 Mar 17, 2006 page 827 of 926 REJ09B0283-0300 Section 22 Power-Down Modes Table 22.2 Oscillation Stabilization Time Settings Standby STS3 STS2 STS1 STS0 Time 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32765 65536 131072 262144 524288 * [MHz] 33 -- -- -- -- -- 1.9 15.5 31.0 62.1 0.12 0.50 0.99 1.99 3.97 7.94 15.89 25 -- -- -- -- -- 2.6 20.5 41.0 81.9 0.16 0.66 1.31 2.62 5.24 10.49 20.97 20 -- -- -- -- -- 3.2 25.6 51.2 102.4 0.20 0.82 1.64 3.28 6.55 13.11 26.21 13 -- -- -- -- -- 4.9 39.4 78.8 157.5 0.32 1.26 2.52 5.04 10.08 20.16 40.33 10 -- -- -- -- -- 6.4 51.2 102.4 204.8 0.41 1.64 3.28 6.55 13.11 26.21 52.43 8 -- -- -- -- -- 8.0 64.0 128.0 256.0 0.51 2.05 4.10 8.19 16.38 32.77 65.54 ms Unit s : Recommended time setting Note: * is the frequency divider output. Software Standby Mode Application Example: Figure 22.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Rev. 3.00 Mar 17, 2006 page 828 of 926 REJ09B0283-0300 Section 22 Power-Down Modes Oscillator NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 22.2 Software Standby Mode Application Example 22.2.4 Hardware Standby Mode Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this LSI is in hardware standby mode. Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (for details on the oscillation stabilization time, refer to table 22.2). When the RES pin is Rev. 3.00 Mar 17, 2006 page 829 of 926 REJ09B0283-0300 Section 22 Power-Down Modes subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Hardware Standby Mode Timing: Figure 22.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 22.3 Hardware Standby Mode Timing 22.2.5 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI are retained. After reset clearance, all modules other than the EXDMAC, DMAC, and DTC are in module stop mode. The module registers which are set in module stop mode cannot be read or written to. Rev. 3.00 Mar 17, 2006 page 830 of 926 REJ09B0283-0300 Section 22 Power-Down Modes 22.2.6 All-Module-Clocks-Stop Mode When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF), or for all the on-chip peripheral functions except the 8-bit timer (MSTPCR = H'FFFE), executing a SLEEP instruction while the SSBY bit in SBYCR is cleared to 0 will cause all the on-chip peripheral functions (except the 8-bit timer and watchdog timer), the bus controller, and the I/O ports to stop operating, and a transition to be made to all-module-clocks-stop mode, at the end of the bus cycle. Operation or halting of the 8-bit timer can be selected by means of the MSTP0 bit. All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15 pins), RES pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal program execution state via the exception handling state. All-module-clocks-stop mode is not cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the relevant interrupt is designated as a DTC activation source. When the STBY pin is driven low, a transition is made to hardware standby mode. 22.3 Clock Output Control Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 22.3 shows the state of the pin in each processing state. Table 22.3 Pin State in Each Processing State Register Setting DDR 0 1 1 Normal PSTOP operating state X 0 1 Sleep mode Software standby mode Hardware standby mode All-moduleclocks-stop mode High impedance High impedance output Fixed high output Fixed high High impedance High impedance High impedance Fixed high Fixed high High impedance output High impedance Fixed high Rev. 3.00 Mar 17, 2006 page 831 of 926 REJ09B0283-0300 Section 22 Power-Down Modes 22.4 22.4.1 Usage Notes I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period. 22.4.3 EXDMAC/DMAC/DTC Module Stop Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP12 bits may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, EXDMA Controller, section 7, DMA Controller (DMAC), and section 9, Data Transfer Controller (DTC). 22.4.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the EXDMAC, DMAC, or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 22.4.5 Writing to MSTPCR MSTPCR should only be written to by the CPU. Rev. 3.00 Mar 17, 2006 page 832 of 926 REJ09B0283-0300 Section 23 List of Registers Section 23 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) * Descriptions by functional module, in order of the corresponding section numbers Entries that consist of lines are for separation of the functional modules. * Access to reserved addresses which are not described in this list is prohibited. * When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the presumption of a big-endian system. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * Reserved bits are indicated by in the bit name. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 or 32 bits, bits are described from the MSB side. The order in which bytes are described is on the presumption of a big-endian system. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * For the initial state of each bit, refer to the description of the register in the corresponding section. * The register states described are for the basic operating modes. If there is a specific reset for an on-chip module, refer to the section on that on-chip module. 23.1 Register Addresses (by functional module, in order of the corresponding section numbers) Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. Rev. 3.00 Mar 17, 2006 page 833 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation MRA SAR MRB DAR CRA CRB SEMR EDSAR_0 Data Width 16/32 16/32 16/32 16/32 16/32 16/32 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name DTC mode register A DTC source address register DTC mode register B DTC destination address register DTC transfer count register A DTC transfer count register B Serial expansion mode register*1 EXDMA source address register_0 Bit No. 8 24 8 24 16 18 8 32 32 32 16 16 32 32 32 16 16 32 32 32 16 16 32 32 32 16 16 16 16 16 16 16 16 Address Module H'BC00 to DTC H'BFFF DTC DTC DTC DTC DTC H'FDA8 H'FDC0 H'FDC4 H'FDC8 H'FDCC H'FDCE H'FDD0 H'FDD4 H'FDD8 H'FDDC H'FDDE H'FDE0 H'FDE4 H'FDE8 H'FDEC H'FDEE H'FDF0 H'FDF4 H'FDF8 H'FDFC H'FDFE H'FE00 H'FE02 H'FE04 H'FE06 H'FE08 H'FE0A SCI_2 EXDMAC_0 16 EXDMAC_0 16 EXDMAC_0 16 EXDMAC_0 16 EXDMAC_0 16 EXDMAC_1 16 EXDMAC_1 16 EXDMAC_1 16 EXDMAC_1 16 EXDMAC_1 16 EXDMAC_2 16 EXDMAC_2 16 EXDMAC_2 16 EXDMAC_2 16 EXDMAC_2 16 EXDMAC_3 16 EXDMAC_3 16 EXDMAC_3 16 EXDMAC_3 16 EXDMAC_3 16 INT INT INT INT INT INT 16 16 16 16 16 16 EXDMA destination address register_0 EDDAR_0 EXDMA transfer count register_0 EXDMA mode control register_0 EXDMA address control register_0 EXDMA source address register_1 EDTCR_0 EDMDR_0 EDACR_0 EDSAR_1 EXDMA destination address register_1 EDDAR_1 EXDMA transfer count register_1 EXDMA mode control register_1 EXDMA address control register_1 EXDMA source address register_2 EDTCR_1 EDMDR_1 EDACR_1 EDSAR_2 EXDMA destination address register_2 EDDAR_2 EXDMA transfer count register_2 EXDMA mode control register_2 EXDMA address control register_2 EXDMA source address register_3 EDTCR_2 EDMDR_2 EDACR_2 EDSAR_3 EXDMA destination address register_3 EDDAR_3 EXDMA transfer count register 3 EXDMA mode control register 3 EXDMA address control register 3 Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F EDTCR_3 EDMDR_3 EDACR_3 IPRA IPRB IPRC IPRD IPRE IPRF Rev. 3.00 Mar 17, 2006 page 834 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation IPRG IPRH IPRI IPRJ IPRK ITSR SSIER ISCRH ISCRL IrCR_0 P1DDR P2DDR P3DDR P5DDR P6DDR P7DDR P8DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR PFCR0 PFCR1 PFCR2 PAPCR PBPCR PCPCR PDPCR PEPCR Data Width 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K IRQ pin select register Software standby release IRQ enable register IRQ sense control register H IRQ sense control register L IrDA control register_0 Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 5 data direction register Port 6 data direction register Port 7 data direction register Port 8 data direction register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port E data direction register Port F data direction register Port G data direction register Port function control register 0 Port function control register 1 Port function control register 2 Port A pull-up MOS control register Port B pull-up MOS control register Port C pull-up MOS control register Port D pull-up MOS control register Port E pull-up MOS control register Bit No. 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FE0C H'FE0E H'FE10 H'FE12 H'FE14 H'FE16 H'FE18 H'FE1A H'FE1C H'FE1E H'FE20 H'FE21 H'FE22 H'FE24 H'FE25 H'FE26 H'FE27 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE32 H'FE33 H'FE34 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A Module INT INT INT INT INT INT INT INT INT IrDA_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Rev. 3.00 Mar 17, 2006 page 835 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation P3ODR PAODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 ABWCR ASTCR WTCRAH WTCRAL Data Width 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port 3 open drain control register Port A open drain control register Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer control register_5 Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter_5 Timer general register A_5 Timer general register B_5 Bus width control register Access state control register Wait control register AH Wait control register AL Bit No. 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 Address H'FE3C H'FE3D H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FEC0 H'FEC1 H'FEC2 H'FEC3 Module PORT PORT TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 BSC BSC BSC BSC Rev. 3.00 Mar 17, 2006 page 836 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation WTCRBH WTCRBL RDNCR CSACRH CSACRL Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Wait control register BH Wait control register BL Read strobe timing control register Chip select assertion period control registers H Chip select assertion period control register L Burst ROM interface control register H Burst ROM interface control register L Bus control register RAM emulation register*3 DRAM control register L DRAM access control register Refresh control register Refresh timer counter Refresh time constant register Memory address register 0AH Memory address register 0AL I/O address register 0A Transfer count register 0A Memory address register 0BH Memory address register 0BL I/O address register 0B Transfer count register 0B Memory address register 1AH Memory address register 1AL I/O address register 1A Transfer count register 1A Memory address register 1BH Memory address register 1BL I/O address register 1B Transfer count register 1B DMA write enable register Bit No. 8 8 8 8 8 Address H'FEC4 H'FEC5 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECE H'FED0 H'FED2 H'FED4 H'FED6 H'FED7 H'FEE0 H'FEE2 H'FEE4 H'FEE6 H'FEE8 H'FEEA H'FEEC H'FEEE H'FEF0 H'FEF2 H'FEF4 H'FEF6 H'FEF8 H'FEFA H'FEFC H'FEFE H'FF20 Module BSC BSC BSC BSC BSC BSC BSC BSC FLASH BSC BSC BSC BSC BSC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC BROMCRH 8 BROMCRL BCR RAMER DRAMCR DRACCR REFCR RTCNT RTCOR MAR0AH MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER 8 16 8 16 8/16*2 16 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 Rev. 3.00 Mar 17, 2006 page 837 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation DMATCR Data Width 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name DMA terminal control register DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register H DMA band control register L DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F DTC enable register G DTC vector register Interrupt control register IRQ enable register IRQ status register Standby control register System clock control register System control register Mode control register Module stop control register H Module stop control register L PLL control register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H*4 Next data register L*4 Bit No. 8 Address H'FF21 H'FF22 H'FF23 H'FF24 H'FF25 H'FF26 H'FF27 H'FF28 H'FF29 H'FF2A H'FF2B H'FF2C H'FF2D H'FF2E H'FF30 H'FF31 H'FF32 H'FF34 H'FF3A H'FF3B H'FF3D H'FF3E H'FF40 H'FF41 H'FF45 H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4C H'FF4D Module DMAC DMAC DMAC DMAC DMAC DMAC DMAC DTC DTC DTC DTC DTC DTC DTC DTC INT INT INT SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM PPG PPG PPG PPG PPG PPG PPG PPG DMACR_0A 8 DMACR_0B 8 DMACR_1A 8 DMACR_1B 8 DMABCRH DMABCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR INTCR IER ISR SBYCR SCKCR SYSCR MDCR MSTPCRH MSTPCRL PLLCR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL 8 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 3.00 Mar 17, 2006 page 838 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation NDRH NDRL PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR P7DR P8DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PORTH PHDR Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Next data register H*4 Next data register L*4 Port 1 register Port 2 register Port 3 register Port 4 register Port 5 register Port 6 register Port 7 register Port 8 register Port A register Port B register Port C register Port D register Port E register Port F register Port G register Port 1 data register Port 2 data register Port 3 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H register Port H data register Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FF4E H'FF4F H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF55 H'FF56 H'FF57 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF64 H'FF65 H'FF66 H'FF67 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF72 Module PPG PPG PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Rev. 3.00 Mar 17, 2006 page 839 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation PHDDR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRA ADDRAH ADDRAL ADDRB ADDRBH ADDRBL Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 16 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port H data direction register Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 A/D data register A (H8S/2678R Group) A/D data register AH (H8S/2678 Group) A/D data register AL (H8S/2678 Group) A/D data register B (H8S/2678R Group) A/D data register BH (H8S/2678 Group) A/D data register BL (H8S/2678 Group) Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 16 8 8 Address H'FF74 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF90 H'FF91 H'FF92 H'FF92 H'FF93 Module PORT SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 A/D A/D A/D A/D A/D A/D Rev. 3.00 Mar 17, 2006 page 840 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation ADDRC ADDRCH ADDRCL ADDRD ADDRDH ADDRDL ADCSR ADDRE ADCR ADDRF ADDRG ADDRH ADCSR ADCR DADR0 DADR1 DACR01 DADR2 DADR3 DACR23 TCR_0 TCR_1 Data Width 16 8 8 16 8 8 8 16 8 16 16 16 16 16 8 8 8 8 8 8 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name A/D data register C (H8S/2678R Group) A/D data register CH (H8S/2678 Group) A/D data register CL (H8S/2678 Group) A/D data register D (H8S/2678R Group) A/D data register DH (H8S/2678 Group) A/D data register DL (H8S/2678 Group) A/D control/status register (H8S/2678 Group) A/D data register E (H8S/2678R Group) A/D control register (H8S/2678 Group) A/D data register F (H8S/2678R Group) A/D data register G (H8S/2678R Group) A/D data register H (H8S/2678R Group) A/D control/status register (H8S/2678R Group) A/D control register (H8S/2678R Group) D/A data register 0 D/A data register 1 D/A control register 01 D/A data register 2 D/A data register 3 D/A control register 23 Timer control register 0 Timer control register 1 Bit No. 16 8 8 16 8 8 8 16 8 16 16 16 8 8 8 8 8 8 8 8 8 8 Address H'FF94 H'FF94 H'FF95 H'FF96 H'FF96 H'FF97 H'FF98 H'FF98 H'FF99 H'FF9A H'FF9C H'FF9E H'FFA0 H'FFA1 H'FFA4 H'FFA5 H'FFA6 H'FFA8 H'FFA9 H'FFAA H'FFB0 H'FFB1 Module A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D D/A D/A D/A D/A D/A D/A TMR_0 TMR_1 Rev. 3.00 Mar 17, 2006 page 841 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCSR Data Width 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 Register Name Timer control/status register 0 Timer control/status register 1 Time constant register A0 Time constant register A1 Time constant register B0 Time constant register B1 Timer counter 0 Timer counter 1 Timer control/status register Bit No. 8 8 8 8 8 8 8 8 8 Address H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 Module TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 H'FFBC*4 WDT (Write) H'FFBC (Read) Timer counter TCNT 8 H'FFBC*4 WDT (Write) H'FFBD (Read) 16 2 Reset control/status register RSTCSR 8 H'FFBE*4 WDT (Write) H'FFBF (Read) 16 2 Timer start register Timer synchronous register Flash memory control register 1*3 Flash memory control register 2*3 Erase block register 1*3 Erase block register 2*3 Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 TSTR TSYR FLMCR1 FLMCR2 EBR1 EBR2 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 8 8 8 8 8 8 8 8 8 8 8 8 16 16 H'FFC0 H'FFC1 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 TPU TPU FLASH FLASH FLASH FLASH TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 16 16 8 8 8 8 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 3.00 Mar 17, 2006 page 842 of 926 REJ09B0283-0300 Section 23 List of Registers Abbreviation TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status rgister_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Bit No. 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 Address H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA Module TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 Notes: 1. Not available in the H8S/2678 Group. 2. In the H8S/2678 Group: 8 bits, in the H8S/2678R Group: 16 bits. 3. Register of the flash memory version. Not available in the masked ROM version and ROM-less version. 4. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. 5. For writing, refer to section 14.6.1, Notes on Register Access. Rev. 3.00 Mar 17, 2006 page 843 of 926 REJ09B0283-0300 Section 23 List of Registers 23.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation MRA SAR Bit 7 AM1 -- -- -- MRB DAR CHNE -- -- -- CRA -- -- -- CRB -- -- -- SEMR*8 -- Bit 6 SM0 -- -- -- DISEL -- -- -- -- -- -- -- -- -- -- Bit 5 DM1 -- -- -- CHNS -- -- -- -- -- -- -- -- -- -- Bit 4 DM0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 MD1 -- -- -- -- -- -- -- -- -- -- -- -- -- ABCS Bit 2 MD0 -- -- -- -- -- -- -- -- -- -- -- -- -- ACS2 Bit 1 DTS -- -- -- -- -- -- -- -- -- -- -- -- -- ACS1 Bit 0 Sz -- -- -- -- -- -- -- -- -- -- -- -- -- ACS0 SCI_2 Smart card interface 2 EXDMAC_0 Module DTC* 9 EDSAR_0 EDDAR_0 EDTCR_0 EDMDR_0 -- -- -- EDA EDIE -- -- -- BEF IRF SAT0 DAT0 -- -- -- BEF IRF SAT0 DAT0 -- -- -- EDRAKE TCEIE SARIE DARIE -- -- -- EDRAKE TCEIE SARIE DARIE -- -- -- ETENDE SDIR SARA4 DARA4 -- -- -- ETENDE SDIR SARA4 DARA4 -- -- -- EDREQS DTSIZE SARA3 DARA3 -- -- -- EDREQS DTSIZE SARA3 DARA3 -- -- -- AMS BGUP SARA2 DARA2 -- -- -- AMS BGUP SARA2 DARA2 -- -- -- MDS1 -- SARA1 DARA1 -- -- -- MDS1 -- SARA1 DARA1 -- -- -- MDS0 -- SARA0 DARA0 -- -- -- MDS0 -- SARA0 DARA0 EDACR_0 SAT1 DAT1 EDSAR_1 EDDAR_1 EDTCR_1 EDMDR_1 -- -- -- EDA EDIE EXDMAC_1 EDACR_1 SAT1 DAT1 Rev. 3.00 Mar 17, 2006 page 844 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation EDSAR_2 EDDAR_2 EDTCR_2 EDMDR_2 Bit 7 -- -- -- EDA EDIE Bit 6 -- -- -- BEF IRF SAT0 DAT0 -- -- -- BEF IRF SAT0 DAT0 IPRA14 IPRA6 IPRB14 IPRB6 IPRC14 IPRC6 IPRD14 IPRD6 IPRE14 IPRE6 IPRF14 IPRF6 IPRG14 IPRG6 IPRH14 IPRH6 IPRI14 IPRI6 IPRJ14 IPRJ6 IPRK14 IPRK6 Bit 5 -- -- -- EDRAKE TCEIE SARIE DARIE -- -- -- EDRAKE TCEIE SARIE DARIE IPRA13 IPRA5 IPRB13 IPRB5 IPRC13 IPRC5 IPRD13 IPRD5 IPRE13 IPRE5 IPRF13 IPRF5 IPRG13 IPRG5 IPRH13 IPRH5 IPRI13 IPRI5 IPRJ13 IPRJ5 IPRK13 IPRK5 Bit 4 -- -- -- ETENDE SDIR SARA4 DARA4 -- -- -- ETENDE SDIR SARA4 DARA4 IPRA12 IPRA4 IPRB12 IPRB4 IPRC12 IPRC4 IPRD12 IPRD4 IPRE12 IPRE4 IPRF12 IPRF4 IPRG12 IPRG4 IPRH12 IPRH4 IPRI12 IPRI4 IPRJ12 IPRJ4 IPRK12 IPRK4 Bit 3 -- -- -- EDREQS DTSIZE SARA3 DARA3 -- -- -- EDREQS DTSIZE SARA3 DARA3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- AMS BGUP SARA2 DARA2 -- -- -- AMS BGUP SARA2 DARA2 IPRA10 IPRA2 IPRB10 IPRB2 IPRC10 IPRC2 IPRD10 IPRD2 IPRE10 IPRE2 IPRF10 IPRF2 IPRG10 IPRG2 IPRH10 IPRH2 IPRI10 IPRI2 IPRJ10 IPRJ2 IPRK10 IPRK2 Bit 1 -- -- -- MDS1 -- SARA1 DARA1 -- -- -- MDS1 -- SARA1 DARA1 IPRA9 IPRA1 IPRB9 IPRB1 IPRC9 IPRC1 IPRD9 IPRD1 IPRE9 IPRE1 IPRF9 IPRF1 IPRG9 IPRG1 IPRH9 IPRH1 IPRI9 IPRI1 IPRJ9 IPRJ1 IPRK9 IPRK1 Bit 0 -- -- -- MDS0 -- SARA0 DARA0 -- -- -- MDS0 -- SARA0 DARA0 IPRA8 IPRA0 IPRB8 IPRB0 IPRC8 IPRC0 IPRD8 IPRD0 IPRE8 IPRE0 IPRF8 IPRF0 IPRG8 IPRG0 IPRH8 IPRH0 IPRI8 IPRI0 IPRJ8 IPRJ0 IPRK8 IPRK0 Module EXDMAC_2 EDACR_2 SAT1 DAT1 EDSAR_3 EDDAR_3 EDTCR_3 EDMDR_3 -- -- -- EDA EDIE EXDMAC_3 EDACR_3 SAT1 DAT1 IPRA -- -- INT IPRB -- -- IPRC -- -- IPRD -- -- IPRE -- -- IPRF -- -- IPRG -- -- IPRH -- -- IPRI -- -- IPRJ -- -- IPRK -- -- Rev. 3.00 Mar 17, 2006 page 845 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation ITSR Bit 7 ITS15 ITS7 Bit 6 ITS14 ITS6 SSI14 SSI6 Bit 5 ITS13 ITS5 SSI13 SSI5 Bit 4 ITS12 ITS4 SSI12 SSI4 Bit 3 ITS11 ITS3 SSI11 SSI3 Bit 2 ITS10 ITS2 SSI10 SSI2 Bit 1 ITS9 ITS1 SSI9 SSI1 Bit 0 ITS8 ITS0 SSI8 SSI0 Module INT SSIER SSI15 SSI7 ISCRH IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ5SCA IRQ1SCA -- P12DDR P22DDR P32DDR P52DDR P62DDR P72DDR P82DDR PA2DDR PB2DDR PC2DDR PD2DDR PE2DDR PF2DDR PG2DDR CS2E A18E LWROE PA2PCR PB2PCR PC2PCR PD2PCR PE2PCR P32ODR PA2ODR IRQ8SCB IRQ4SCB IRQ0SCB -- P11DDR P21DDR P31DDR P51DDR P61DDR P71DDR P81DDR PA1DDR PB1DDR PC1DDR PD1DDR PE1DDR PF1DDR PG1DDR CS1E A17E OES PA1PCR PB1PCR PC1PCR PD1PCR PE1PCR P31ODR PA1ODR IRQ8SCA IRQ4SCA IRQ0SCA -- P10DDR P20DDR P30DDR P50DDR P60DDR P70DDR P80DDR PA0DDR PB0DDR PC0DDR PD0DDR PE0DDR PF0DDR PG0DDR CS0E A16E DMACS PA0PCR PB0PCR PC0PCR PD0PCR PE0PCR P30ODR PA0ODR IrDA_0 PORT ISCRL IRQ7SCB IRQ3SCB IRQ7SCA IRQ3SCA IrCKS2 P16DDR P26DDR -- -- -- -- -- PA6DDR PB6DDR PC6DDR PD6DDR PE6DDR PF6DDR PG6DDR CS6E A22E -- PA6PCR PB6PCR PC6PCR PD6PCR PE6PCR -- PA6ODR IRQ6SCB IRQ2SCB IrCKS1 P15DDR P25DDR P35DDR -- P65DDR P75DDR P85DDR PA5DDR PB5DDR PC5DDR PD5DDR PE5DDR PF5DDR PG5DDR CS5E A21E -- PA5PCR PB5PCR PC5PCR PD5PCR PE5PCR P35ODR PA5ODR IRQ6SCA IRQ2SCA IrCKS0 P14DDR P24DDR P34DDR -- P64DDR P74DDR P84DDR PA4DDR PB4DDR PC4DDR PD4DDR PE4DDR PF4DDR PG4DDR CS4E A20E -- PA4PCR PB4PCR PC4PCR PD4PCR PE4PCR P34ODR PA4ODR IRQ5SCB IRQ1SCB -- P13DDR P23DDR P33DDR P53DDR P63DDR P73DDR P83DDR PA3DDR PB3DDR PC3DDR PD3DDR PE3DDR PF3DDR PG3DDR CS3E A19E ASOE PA3PCR PB3PCR PC3PCR PD3PCR PE3PCR P33ODR PA3ODR IrCR_0 P1DDR P2DDR P3DDR P5DDR P6DDR P7DDR P8DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR PFCR0 PFCR1 PFCR2 PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR IrE P17DDR P27DDR -- -- -- -- -- PA7DDR PB7DDR PC7DDR PD7DDR PE7DDR PF7DDR -- CS7E A23E -- PA7PCR PB7PCR PC7PCR PD7PCR PE7PCR -- PA7ODR Rev. 3.00 Mar 17, 2006 page 846 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 Bit 7 CCLR2 -- IOB3 IOD3 TTGE -- Bit15 Bit7 Bit 6 CCLR1 -- IOB2 IOD2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit 5 CCLR0 BFB IOB1 IOD1 -- -- Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit 4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit 3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit 2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit 0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Module TPU_3 TGRA_3 Bit15 Bit7 TGRB_3 Bit15 Bit7 TGRC_3 Bit15 Bit7 TGRD_3 Bit15 Bit7 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 -- -- IOB3 TTGE TCFD Bit15 Bit7 TPU_4 TGRA_4 Bit15 Bit7 TGRB_4 Bit15 Bit7 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 -- -- IOB3 TTGE TCFD Bit15 Bit7 TPU_5 Rev. 3.00 Mar 17, 2006 page 847 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation TGRA_5 Bit 7 Bit15 Bit7 Bit 6 Bit14 Bit6 Bit14 Bit6 ABW6 AST6 W72 W52 W32 W12 RDN6 CSXH6 CSXT6 BSTS02 BSTS12 BREQ0E -- -- RAST RCDM -- -- CMIE CBRM Bit6 Bit6 -- Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 -- Bit6 Bit 5 Bit13 Bit5 Bit13 Bit5 ABW5 AST5 W71 W51 W31 W11 RDN5 CSXH5 CSXT5 BSTS01 BSTS11 -- -- -- -- DDS TPC1 -- RCW1 RLW1 Bit5 Bit5 -- Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 -- Bit5 Bit 4 Bit12 Bit4 Bit12 Bit4 ABW4 AST4 W70 W50 W30 W10 RDN4 CSXH4 CSXT4 BSTS00 BSTS10 IDLC -- -- CAST EDDS TPC0 -- RCW0 RLW0 Bit4 Bit4 -- Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 -- Bit4 Bit 3 Bit11 Bit3 Bit11 Bit3 ABW3 AST3 -- -- -- -- RDN3 CSXH3 CSXT3 -- -- ICIS1 -- RAMS -- -- SDWCD* CKSPE*8 -- SLFRF Bit3 Bit3 -- Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 -- Bit3 8 Bit 2 Bit10 Bit2 Bit10 Bit2 ABW2 AST2 W62 W42 W22 W02 RDN2 CSXH2 CSXT2 -- -- ICIS0 8 ICIS2* Bit 1 Bit9 Bit1 Bit9 Bit1 ABW1 AST1 W61 W41 W21 W01 RDN1 CSXH1 CSXT1 BSWD01 BSWD11 WDBE -- RAM1 RMTS1 MXC1 RCD1 RDXC1*8 RTCK1 TPCS1 Bit1 Bit1 -- Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 -- Bit1 Bit 0 Bit8 Bit0 Bit8 Bit0 ABW0 AST0 W60 W40 W20 W00 RDN0 CSXH0 CSXT0 BSWD00 BSWD10 WAITE -- RAM0 RMTS0 MXC0 RCD0 RDXC0*8 RTCK0 TPCS0 Bit0 Bit0 -- Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 -- Bit0 Module TPU_5 TGRB_5 Bit15 Bit7 ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH CSACRL BROMCRH BROMCRL BCR ABW7 AST7 -- -- -- -- RDN7 CSXH7 CSXT7 BSRM0 BSRM1 BRLE -- BSC RAMER*7 DRAMCR -- 0EE BE RAM2 RMTS2 MXC2 -- -- RTCK2 TPCS2 Bit2 Bit2 -- Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 -- Bit2 FLASH BSC DRACCR*1 DRMI -- REFCR CMF RFSHE RTCNT RTCOR MAR_0AH Bit7 Bit7 -- Bit7 DMAC MAR_0AL Bit15 Bit7 IOAR_0A Bit15 Bit7 ETCR_0A Bit15 Bit7 MAR_0BH -- Bit7 Rev. 3.00 Mar 17, 2006 page 848 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation MAR_0BL Bit 7 Bit15 Bit7 Bit 6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 -- Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 -- Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 -- -- DTID SAID DTID DAID DTID SAID DTID DAID FAE0 FAE0 DTE1A DTE1 Bit 5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 -- Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 -- Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 -- TEE1 RPE SAIDE RPE DAIDE RPE SAIDE RPE DAIDE SAE1 -- DTE0B DTME0 Bit 4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 -- Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 -- Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 -- TEE0 DTDIR BLKDIR DTDIR -- DTDIR BLKDIR DTDIR -- SAE0 -- DTE0A DTE0 Bit 3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 -- Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 -- Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 WE1B -- DTF3 BLKE DTF3 DTF3 DTF3 BLKE DTF3 DTF3 DTA1B DTA1 DTIE1B DTIE1B Bit 2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 -- Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 -- Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 WE1A -- DTF2 -- DTF2 DTF2 DTF2 -- DTF2 DTF2 DTA1A -- DTIE1A DTIE1A Bit 1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 -- Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 -- Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 WE0B -- DTF1 -- DTF1 DTF1 DTF1 -- DTF1 DTF1 DTA0B DTA0 DTIE0B DTIE0B Bit 0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 -- Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 -- Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 WE0A -- DTF0 -- DTF0 DTF0 DTF0 -- DTF0 DTF0 DTA0A -- DTIE0A DTIE0A Module DMAC IOAR_0B Bit15 Bit7 ETCR_0B Bit15 Bit7 MAR_1AH -- Bit7 MAR_1AL Bit15 Bit7 IOAR_1A Bit15 Bit7 ETCR_1A Bit15 Bit7 MAR_1BH -- Bit7 MAR_1BL Bit15 Bit7 IOAR_1B Bit15 Bit7 ETCR_1B Bit15 Bit7 DMAWER DMATCR -- -- DMACR_0A*11 DTSZ DMACR_0A*12 DTSZ DMACR_0B*11 DTSZ DMACR_0B*12 -- DMACR_1A*11 DTSZ DMACR_1A*12 DTSZ DMACR_1B*11 DTSZ DMACR_1B*12 -- DMABCRH*11 DMABCRH*12 DMABCRL*11 DMABCRL* 12 FAE1 FAE1 DTE1B DTME1 Rev. 3.00 Mar 17, 2006 page 849 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR INTCR IER Bit 7 DTCEA7 DTCEB7 -- DTCED7 DTCEE7 DTCEF7 DTCEG7 SWDTE -- IRQ15E IRQ7E Bit 6 DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTCEF6 DTCEG6 DTVEC6 -- IRQ14E IRQ6E IRQ14F IRQ6F OPE -- -- -- MSTP14 MSTP6 -- G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 -- -- P16 P26 -- P46 P56 Bit 5 DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTCEF5 -- DTVEC5 INTM1 IRQ13E IRQ5E IRQ13F IRQ5F -- -- MACS -- MSTP13 MSTP5 -- G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 -- -- P15 P25 P35 P45 P55 Bit 4 DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTCEF4 -- DTVEC4 INTM0 IRQ12E IRQ4E IRQ12F IRQ4F -- -- -- -- MSTP12 MSTP4 -- G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 -- -- P14 P24 P34 P44 P54 Bit 3 DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTCEF3 -- DTVEC3 NMIEG IRQ11E IRQ3E IRQ11F IRQ3F STS3 STCS FLSHE -- MSTP11 MSTP3 -- G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 P13 P23 P33 P43 P53 Bit 2 DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTCEF2 -- DTVEC2 -- IRQ10E IRQ2E IRQ10F IRQ2F STS2 SCK2 -- MDS2 MSTP10 MSTP2 -- G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 P12 P22 P32 P42 P52 Bit 1 DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTCEF1 -- DTVEC1 -- IRQ9E IRQ1E IRQ9F IRQ1F STS1 SCK1 EXPE MDS1 MSTP9 MSTP1 STC1 G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 P11 P21 P31 P41 P51 Bit 0 DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTCEF0 -- DTVEC0 -- IRQ8E IRQ0E IRQ8F IRQ0F STS0 SCK0 RAME MDS0 MSTP8 MSTP0 STC0 G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 P10 P20 P30 P40 P50 Module DTC*10 INT ISR IRQ15F IRQ7F SBYCR SCKCR SYSCR MDCR MSTPCRH MSTPCRL PLLCR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL PORT1 PORT2 PORT3 PORT4 PORT5 SSBY PSTOP -- -- ACSE MSTP7 -- G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 -- -- P17 P27 -- P47 P57 SYSTEM PPG PORT Rev. 3.00 Mar 17, 2006 page 850 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation PORT6 PORT7 PORT8 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR P7DR P8DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PORTH PHDR PHDDR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 Bit 7 -- -- -- PA7 PB7 PC7 PD7 PE7 PF7 -- P17DR P27DR -- -- -- -- -- PA7DR PB7DR PC7DR PD7DR PE7DR PF7DR -- -- -- -- C/A/ 2 GM* Bit7 TIE Bit7 TDRE Bit7 -- Bit 6 -- -- -- PA6 PB6 PC6 PD6 PE6 PF6 PG6 P16DR P26DR -- -- -- -- -- PA6DR PB6DR PC6DR PD6DR PE6DR PF6DR PG6DR -- -- -- CHR/ 3 BLK* Bit6 RIE Bit6 RDRF Bit6 -- Bit 5 P65 P75 P85 PA5 PB5 PC5 PD5 PE5 PF5 PG5 P15DR P25DR P35DR -- P65DR P75DR P85DR PA5DR PB5DR PC5DR PD5DR PE5DR PF5DR PG5DR -- -- -- PE Bit5 TE Bit5 ORER Bit5 -- Bit 4 P64 P74 P84 PA4 PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR -- P64DR P74DR P84DR PA4DR PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR -- -- -- O/E Bit4 RE Bit4 FER/ 6 ERS* Bit4 -- Bit 3 P63 P73 P83 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR P73DR P83DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR PH3 PH3DR PH3DDR STOP/ BCP1*4 Bit3 MPIE Bit3 PER Bit3 SDIR Bit 2 P62 P72 P82 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR P72DR P82DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR PH2 PH2DR PH2DDR MP/ 5 BCP0* Bit2 TEIE Bit2 TEND Bit2 SINV Bit 1 P61 P71 P81 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR P71DR P81RD PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR PH1 PH1DR PH1DDR CKS1 Bit1 CKE1 Bit1 MPB Bit1 -- Bit 0 P60 P70 P80 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR P70DR P80DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR PG0DR PH0 PH0DR PH0DDR CKS0 Bit0 CKE0 Bit0 MPBT Bit0 SMIF Module PORT SCI_0, Smart card interface 0 Rev. 3.00 Mar 17, 2006 page 851 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRA TDRE Bit7 -- AD9 AD1 ADDRB AD9 AD1 ADDRC AD9 AD1 ADDRD AD9 AD1 ADDRE* 8 Bit 7 C/A/ GM*2 Bit7 TIE Bit7 TDRE Bit7 -- C/A/ GM*2 Bit7 TIE Bit 6 CHR/ 3 BLK* Bit6 RIE Bit6 RDRF Bit6 -- CHR/ 3 BLK* Bit6 RIE Bit 5 PE Bit5 TE Bit5 ORER Bit5 -- PE Bit5 TE Bit 4 O/E Bit4 RE Bit4 FER/ 6 ERS* Bit4 -- O/E Bit4 RE Bit 3 STOP/ BCP1*4 Bit3 MPIE Bit3 PER Bit3 SDIR STOP/ BCP1*4 Bit3 MPIE Bit 2 MP/ 5 BCP0* Bit2 TEIE Bit2 TEND Bit2 SINV MP/ 5 BCP0* Bit2 TEIE Bit 1 CKS1 Bit1 CKE1 Bit1 MPB Bit1 -- CKS1 Bit1 CKE1 Bit 0 CKS0 Bit0 CKE0 Bit0 MPBT Bit0 SMIF CKS0 Bit0 CKE0 Module SCI_1, Smart card interface 1 SCI_2, Smart card interface 2 RDRF Bit6 -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 ORER Bit5 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- AD7 -- ADST --*9/ 8 SCANE* FER/ 6 ERS* Bit4 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN* / 8 --* 9 PER Bit3 SDIR AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- AD5 -- CKS* / 8 CH3* 9 TEND Bit2 SINV AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- AD4 -- CH2 CH3*9/ 8 CKS0* MPB Bit1 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- MPBT Bit0 SMIF AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- A/D AD9 AD1 ADDRF*8 AD9 AD1 ADDRG*8 AD9 AD1 ADDRH*8 AD9 AD1 ADCSR ADCR ADF TRGS1 --*9/ 8 SCANS* CKS1 Rev. 3.00 Mar 17, 2006 page 852 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation DADR0 DADR1 DACR01 DADR2 DADR3 DACR23 TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCSR TCNT RSTCSR TSTR TSYR FLMCR1*7 FLMCR2*7 EBR1*7 EBR2*7 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 Bit 7 Bit7 Bit7 DAOE1 Bit7 Bit7 DAOE3 CMIEB CMIEB CMFB CMFB Bit7 Bit7 Bit7 Bit7 Bit7 Bit7 OVF Bit7 WOVF -- -- FWE FLER EB7 -- CCLR2 -- IOB3 IOD3 TTGE -- Bit15 Bit7 Bit 6 Bit6 Bit6 DAOE0 Bit6 Bit6 DAOE2 CMIEA CMIEA CMFA CMFA Bit6 Bit6 Bit6 Bit6 Bit6 Bit6 WT/IT Bit6 RSTE -- -- SWE -- EB6 -- CCLR1 -- IOB2 IOD2 -- -- Bit14 Bit6 Bit14 Bit6 Bit 5 Bit5 Bit5 DAE Bit5 Bit5 DAE OVIE OVIE OVF OVF Bit5 Bit5 Bit5 Bit5 Bit5 Bit5 TME Bit5 -- CST5 SYNC5 ESU -- EB5 EB13 CCLR0 BFB IOB1 IOD1 -- -- Bit13 Bit5 Bit13 Bit5 Bit 4 Bit4 Bit4 -- Bit4 Bit4 -- CCLR1 CCLR1 ADTE -- Bit4 Bit4 Bit4 Bit4 Bit4 Bit4 -- Bit4 -- CST4 SYNC4 PSU -- EB4 EB12 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit 3 Bit3 Bit3 -- Bit3 Bit3 -- CCLR0 CCLR0 OS3 OS3 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3 -- Bit3 -- CST3 SYNC3 EV -- EB3 EB11 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit11 Bit3 Bit11 Bit3 Bit 2 Bit2 Bit2 -- Bit2 Bit2 -- CKS2 CKS2 OS2 OS2 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2 CKS2 Bit2 -- CST2 SYNC2 PV -- EB2 EB10 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit10 Bit2 Bit10 Bit2 Bit 1 Bit1 Bit1 -- Bit1 Bit1 -- CKS1 CKS1 OS1 OS1 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1 CKS1 Bit1 -- CST1 SYNC1 E -- EB1 EB9 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit 0 Bit0 Bit0 -- Bit0 Bit0 -- CKS0 CKS0 OS0 OS0 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0 CKS0 Bit0 -- CST0 SYNC0 P -- EB0 EB8 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Module D/A TMR_0 TMR_1 WDT TPU FLASH TPU_0 TGRA_0 Bit15 Bit7 Rev. 3.00 Mar 17, 2006 page 853 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation TGRB_0 Bit 7 Bit15 Bit7 Bit 6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 -- IOB2 -- -- Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit 5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 -- IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit 4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 -- IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit 3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 -- -- Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit 2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 -- -- Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit 1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit 0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Module TPU_0 TGRC_0 Bit15 Bit7 TGRD_0 Bit15 Bit7 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 -- -- IOB3 TTGE TCFD Bit15 Bit7 TPU_1 TGRA_1 Bit15 Bit7 TGRB_1 Bit15 Bit7 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 -- -- IOB3 TTGE TCFD Bit15 Bit7 TPU_2 TGRA_2 Bit15 Bit7 TGRB_2 Bit15 Bit7 Notes: 1. 2. 3. 4. 5. 6. 7. In the H8S/2678 Group: 8 bits, in the H8S/2678R Group: 16 bits. Functions as C/A for SCI use, and as GM for smart card interface use. Functions as CHR for SCI use, and as BLK for smart card interface use. Functions as STOP for SCI use, and as BCP1 for smart card interface use. Functions as MP for SCI use, and as BCP0 for smart card interface use. Functions as FER for SCI use, and as ERS for smart card interface use. Register of the flash memory version. Not available in the masked ROM version and ROM-less version. 8. Not available in the H8S/2678 Group. 9. Not available in the H8S/2678R Group. Rev. 3.00 Mar 17, 2006 page 854 of 926 REJ09B0283-0300 Section 23 List of Registers 10. Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 11. For short address mode 12. For full address mode Rev. 3.00 Mar 17, 2006 page 855 of 926 REJ09B0283-0300 Section 23 List of Registers 23.3 Register States in Each Operating Mode Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized SCI2 EXDMA_C Module DTC Register Abbreviation MRA SAR MRB DAR CRA CRB SEMR*1 EDSAR_0 EDDAR_0 EDTCR_0 EDMDR_0 EDACR_0 EDSAR_1 EDDAR_1 EDTCR_1 EDMDR_1 EDACR_1 EDSAR_2 EDDAR_2 EDTCR_2 EDMDR_2 EDACR_2 EDSAR_3 EDDAR_3 EDTCR_3 EDMDR_3 EDACR_3 IPRA IPRB IPRC IPRD IPRE IPRF Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized EXDMA_1 EXDMA_2 EXDMA_3 INT Rev. 3.00 Mar 17, 2006 page 856 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation IPRG IPRH IPRI IPRJ IPRK ITSR SSIER ISCRH ISCRL IrCR_0 P1DDR P2DDR P3DDR P5DDR P6DDR P7DDR P8DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR PFCR0 PFCR1 PFCR2 PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IrDA_0 PORT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module INT Rev. 3.00 Mar 17, 2006 page 857 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 ABWCR ASTCR WTCRAH WTCRAL WTCRBH WTCRBL RDNCR CSACRH HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized BSC TPU_5 TPU_4 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module TPU_3 Rev. 3.00 Mar 17, 2006 page 858 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation CSACRL BROMCRH BROMCRL BCR RAMER* 2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module BSC FLASH BSC DRAMCR DRACCR REFCR RTCNT RTCOR MAR_0AH MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCRH DMABCRL DMAC Rev. 3.00 Mar 17, 2006 page 859 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR INTCR IER ISR SBYCR SCKCR SYSCR MDCR MSTPCRH MSTPCRL PLLCR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- PORT PPG SYSTEM INT Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module DTC Rev. 3.00 Mar 17, 2006 page 860 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation PORT7 PORT8 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR P7DR P8DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PORTH PHDR PHDDR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reset -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module PORT Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- -- -- Initialized -- Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 3.00 Mar 17, 2006 page 861 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRA ADDRB ADDRC ADDRD ADDRE*1 ADDRF*1 ADDRG*1 ADDRH*1 ADCSR ADCR DADR0 DADR1 DACR01 DADR2 DADR3 DACR23 TCR_0 TCR_1 TCSR_0 TCSR_1 HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop All Module Clock Stop Software Hardware Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_0 TMR_1 D/A A/D SCI_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module SCI_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 3.00 Mar 17, 2006 page 862 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCSR TCNT RSTCSR TSTR TSYR FLMCR1* FLMCR2* 2 EBR1* 2 EBR2* 2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module TMR_0 TMR_1 WDT TPU FLASH 2 TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TPU_0 TPU_1 Rev. 3.00 Mar 17, 2006 page 863 of 926 REJ09B0283-0300 Section 23 List of Registers Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 HighSpeed -- -- -- -- -- -- -- -- Clock Division -- -- -- -- -- -- -- -- Module Stop -- -- -- -- -- -- -- -- All Module Clock Stop -- -- -- -- -- -- -- -- Software Hardware Standby Standby -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- Module TPU_2 Notes: 1. Not available in the H8S/2678 Group. 2. Register of the flash memory version. Not available in the masked ROM version and ROM-less version. Rev. 3.00 Mar 17, 2006 page 864 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 4, P54 to P57) Input voltage (port 4, P54 to P57) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC PLLVCC Vin Vin Vref AVCC VAN Topr -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to + 4.6* -0.3 to AVCC + 0.3 Regular specifications: -20 to + 75* Wide-range specifications: -40 to + 85 -55 to + 125* V V V V V C C C Value -0.3 to + 4.6* Unit V Storage temperature Tstg Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note: * F-ZTAT version: Ranges of power supply voltage and analog power supply voltage: -0.3 to 4.0 V Ranges of operating temperature when flash memory is programmed/erased: Regular specifications: 0 to +75C Wide-range specifications: 0 to +85C Rev. 3.00 Mar 17, 2006 page 865 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics 24.2 DC Characteristics Table 24.2 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, 1 VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Schmitt Ports 1, 2, 2 trigger input P50 to P53* , *2, 8*2, voltage ports 6 2 2 PF1* , PF2* , 2 2 PH2* , PH3* P54 to P57* 2 Symbol VT - Min VCC x 0.2 Typ -- Max -- Test Unit Conditions V VT + -- - -- -- -- -- -- VCC x 0.7 -- -- -- VCC + 0.3 V V V V V VT - VT VT VT Input high voltage STBY, MD2 to MD0, 4 DCTL* RES, NMI EXTAL Port 3, 3 P50 to P53* , 3 ports 6 to 8* , *3 ports A to H Port 4, 3 P54 to P57* Input low voltage RES, STBY, MD2 to MD0, 4 DCTL* NMI, EXTAL Ports 3 to 8, 3 ports A to H* Output high All output pins voltage VOH VIL VIH - + + + VCC x 0.07 AVCC x 0.2 -- AVCC x 0.7 V VT - VT - AVCC x 0.07 -- VCC x 0.9 VCC x 0.9 VCC x 0.7 VCC x 0.7 -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V AVCC x 0.7 -0.3 -- -- AVCC + 0.3 V VCC x 0.1 V -0.3 -0.3 VCC - 0.5 VCC - 1.0 -- -- -- -- VCC x 0.2 VCC x 0.2 -- -- V V V V IOH = -200 A IOH = -1 mA Rev. 3.00 Mar 17, 2006 page 866 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Test Unit Conditions V A A IOL = 1.6 mA Vin = 0.5 to VCC - 0.5 V Item Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0, 4 DCTL* Port 4, P54 to P57 Symbol VOL |Iin| Min -- -- -- Typ -- -- -- Max 0.4 10.0 1.0 -- -- 1.0 A Vin = 0.5 to AVCC - 0.5 V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. When used as IRQ0 to IRQ15. 3. When used as other than IRQ0 to IRQ15. 4. Not supported in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 867 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Table 24.3 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, 1 VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Three-state leakage current (off state) Ports 1 to 3, P50 to P53, ports 6 to 8, ports A to H Symbol | ITSI | Min -- Typ -- Max 1.0 Test Unit Conditions A Vin = 0.5 to VCC - 0.5 V Input pull-up Ports A to E MOS current Input RES capacitance NMI All input pins except RES and NMI -Ip 10 -- 300 A VCC = 2.7 to 3.6 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C Cin -- -- -- -- -- -- 30 30 15 pF pF pF 4 Current Normal operation ICC* consamption *2 -- 80 150 (3.3 V) 70 125 (3.3 V) 0.01 -- 10 80 mA f = 33 MHz Sleep mode Standby mode* 3 -- -- -- mA A A A mA A mA A V f = 33 MHz Ta 50C 50C < Ta All module clocks 5 stopped* Analog power supply current Reference power supply current During A/D and D/A conversion Idle During A/D and D/A conversion Idle VRAM AICC AICC -- -- -- -- -- 2.0 50 125 (3.3 V) 0.2 2.0 (3.0 V) 0.01 5.0 1.4 4.0 (3.0 V) 0.01 -- 5.0 -- RAM standby voltage Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev. 3.00 Mar 17, 2006 page 868 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics 2. Current dissipation values are for VIHmin = VCC - 0.5 V and VILmax = 0.5 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM VCC < 3.0 V, VIHmin = VCC x 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 1.0 (mA) + 1.2 (mA/(MHz x V)) x VCC x f (normal operation) ICCmax = 1.0 (mA) + 1.0 (mA/(MHz x V)) x VCC x f (sleep mode) 5. The values are for reference. Table 24.4 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins All output pins Total of all output pins Symbol IOL IOL -IOH -IOH Min -- -- -- -- Typ -- -- -- -- Max 2.0 80 2.0 40 Unit mA mA mA mA Caution: To protect the LSI's reliability, do not exceed the output current values in table 24.3. Note: * If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. Rev. 3.00 Mar 17, 2006 page 869 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics 24.3 AC Characteristics 3V RL C = 50 pF: ports A to H C = 30 pF: ports 1 to 3, P50 to P53, ports 6 to 8 RL = 2.4 k RH = 12 k Input/output timing measurement level: 1.5 V (VCC = 2.7 V to 3.6 V) LSI output pin C RH Figure 24.1 Output Load Circuit Rev. 3.00 Mar 17, 2006 page 870 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Clock Timing Table 24.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output delay stabilization time Clock phase difference* Clock pulse high width (SDRAM)* Clock pulse low width (SDRAM)* Clock rise time (SDRAM)* Clock fall time (SDRAM)* Note: * Symbol Min tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tcdif tSDCH tSDCL tsdcr tsdcf 30.3 10 10 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Unit ns ns ns ns ns ms ms s Figure 24.4 (1) Figure 24.4 (2) Figure 24.4 (1) Figure 24.3 Figure 24.3 Figure 24.3 Figure 24.3 Figure 24.3 Test Conditions Figure 24.2 Figure 24.2 1/4 x tcyc - 3 1/4 x tcyc + 3 ns 10 10 -- -- -- -- 5 5 ns ns ns ns Not supported in the H8S/2678 Group. tcyc tCH tCf tCL tCr Figure 24.2 System Clock Timing Rev. 3.00 Mar 17, 2006 page 871 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics tcyc tCH tCr tsdcr SDRAM tCf tCL tcdif tsdcf tSDCH tSDCL Figure 24.3 SDRAM Timing* Note: Not supported in the H8S/2678 Group. EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 24.4 (1) Oscillation Stabilization Timing Rev. 3.00 Mar 17, 2006 page 872 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Oscillator NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 SLEEP instruction Figure 24.4 (2) Oscillation Stabilization Timing Rev. 3.00 Mar 17, 2006 page 873 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Control Signal Timing Table 24.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- ns Unit ns tcyc ns Figure 24.6 Test Conditions Figure 24.5 tRESS RES tRESW tRESS Figure 24.5 Reset Input Timing Rev. 3.00 Mar 17, 2006 page 874 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * Necessary for SSIER setting to clear software standby mode. Figure 24.6 Interrupt Input Timing Rev. 3.00 Mar 17, 2006 page 875 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Bus Timing Table 24.7 Bus Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Address delay time Address setup time 1 Address setup time 2 Address setup time 3 Address setup time 4 Address hold time 1 Address hold time 2 Address hold time 3 CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 Read data access time 6 Read data access time 7 Read data access time 8 Address read data access time 1 Address read data access time 2 Address read data access time 3 Address read data access time 4 Address read data access time 5 Symbol tAD tAS1 tAS2 tAS3 tAS4 tAH1 tAH2 tAH3 tCSD1 tCSD2 tCSD3 tASD tRSD1 tRSD2 tRDS1 tRDS2 tRDH1 tRDH2 tAC1 tAC2 tAC3 tAC4 tAC5 tAC6 tAC7 tAC8 tAA1 tAA2 tAA3 tAA4 tAA5 Min -- 0.5 x tcyc - 13 1.0 x tcyc - 13 1.5 x tcyc - 13 2.0 x tcyc - 13 0.5 x tcyc - 8 1.0 x tcyc - 8 1.5 x tcyc - 8 -- -- -- -- -- -- 15 15 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- Max 20 -- -- -- -- -- -- -- 15 15 20 15 15 15 -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 2.0 x tcyc - 20 2.5 x tcyc - 20 1.0 x tcyc - 20 2.0 x tcyc - 20 4.0 x tcyc - 20 3.0 x tcyc - 20 1.0 x tcyc - 20 1.5 x tcyc - 20 2.0 x tcyc - 20 2.5 x tcyc - 20 3.0 x tcyc - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 24.7 to 24.21 Rev. 3.00 Mar 17, 2006 page 876 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Table 24.8 Bus Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time 1 Write data setup time 2 Write data setup time 3 Write data hold time 1 Write data hold time 2 Write data hold time 3 Write command setup time 1 Write command setup time 2 Write command hold time 1 Write command hold time 2 Read command setup time 1 Read command setup time 2 Read command hold time CAS delay time 1 CAS delay time 2 CAS setup time 1 CAS setup time 2 CAS pulse width 1 CAS pulse width 2 CAS precharge time 1 CAS precharge time 2 OE delay time 1 OE delay time 2 Precharge time 1 Precharge time 2 Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS1 tWDS2 tWDS3 tWDH1 tWDH2 tWDH3 tWCS1 tWCS2 tWCH1 tWCH2 tRCS1 tRCS2 tRCH tCASD1 tCASD2 tCSR1 tCSR2 tCASW1 tCASW2 tCPW1 tCPW2 tOED1 tOED2 tPCH1 tPCH2 Min -- -- 1.0 x tcyc - 13 1.5 x tcyc - 13 -- 0.5 x tcyc - 13 1.0 x tcyc - 13 1.5 x tcyc - 13 0.5 x tcyc - 8 1.0 x tcyc - 8 1.5 x tcyc - 8 0.5 x tcyc - 10 1.0 x tcyc - 10 0.5 x tcyc - 10 1.0 x tcyc - 10 1.5 x tcyc - 10 2.0 x tcyc - 10 0.5 x tcyc - 10 -- -- 0.5 x tcyc - 10 1.5 x tcyc - 10 1.0 x tcyc - 20 1.5 x tcyc - 20 1.0 x tcyc - 20 1.5 x tcyc - 20 -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 Max 15 15 -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 15 15 -- -- -- -- -- -- 15 15 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 24.7 to 24.21 Rev. 3.00 Mar 17, 2006 page 877 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Item Self-refresh precharge time 1 Self-refresh precharge time 2 WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Address delay time 2* CS delay time 4* DQM delay time* CKE delay time* Read data setup time 3* Read data hold time 3* Write data delay time 2* Write data hold time 4* Symbol tRPS1 tRPS2 tWTS tWTH tBREQS tBACD tBZD tBRQOD tAD2 tCSD4 tDQMD tCKED tRDS3 tRDH3 tWDD2 tWDH3 Min 2.5 x tcyc - 20 3.0 x tcyc - 20 25 5 30 -- -- -- -- -- -- -- 15 0 -- 2 Max -- -- -- -- -- 15 40 25 16.5 16.5 16.5 16.5 -- -- 31.5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 24.25 Figure 24.26 Figure 24.26 Figure 24.26 Figure 24.27 Figure 24.26 Figure 24.26 Figure 24.26 Figure 24.26 Figure 24.24 Test Conditions Figures 24.22, 24.23 Figure 24.15 Note: * Not supported in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 878 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 AS tAS1 RD Read (RDNn = 1) D15 to D0 tAS1 RD Read (RDNn = 0) D15 to D0 tAS1 HWR, LWR Write D15 to D0 tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tWDD tWSW1 tAC2 tAA3 tRSD1 tAC5 tAA2 tRSD1 tASD tASD T2 tAH1 tRSD1 tRDS1 tRDH1 tRSD2 tRDS2 tRDH2 tWRD2 tWRD2 tAH1 tWDH1 tDACD2 tEDACD2 Figure 24.7 Basic Bus Timing: Two-State Access Rev. 3.00 Mar 17, 2006 page 879 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 AS tAS1 RD Read (RDNn = 1) D15 to D0 tAS1 RD Read (RDNn = 0) D15 to D0 tAS2 HWR, LWR Write D15 to D0 tWDD tRSD1 tRSD1 tASD T2 T3 tASD tAH1 tRSD1 tAC6 tAA4 tRDS1 tRDH1 tRSD2 tAC4 tAA5 tWRD2 tWRD1 tWDS1 tWSW2 tRDS2 tRDH2 tAH1 tWDH1 tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tDACD2 tEDACD2 Figure 24.8 Basic Bus Timing: Three-State Access Rev. 3.00 Mar 17, 2006 page 880 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 T2 Tw T3 A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 tWTS tWTH WAIT tWTS tWTH Figure 24.9 Basic Bus Timing: Three-State Access, One Wait Rev. 3.00 Mar 17, 2006 page 881 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Th tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD AS tAS3 RD Read (RDNn = 1) D15 to D0 tAS3 RD Read (RDNn = 0) D15 to D0 tAS3 HWR, LWR Write D15 to D0 tWDD tWDS2 T1 T2 Tt tASD tAH1 tRSD1 tRSD1 tAH3 tAC5 tRDS1 tRDH1 tRSD1 tRSD2 tAH2 tAC2 tRDS2 tRDH2 tWRD2 tWRD2 tAH3 tWSW1 tWDH3 tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tDACD2 tEDACD2 Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) CS Rev. 3.00 Mar 17, 2006 page 882 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Th tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD AS tAS3 RD Read (RDNn = 1) D15 to D0 tAS3 RD Read (RDNn = 0) D15 to D0 tAS4 HWR, LWR Write D15 to D0 tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tWDD T1 T2 T3 Tt tASD tAH1 tRSD1 tRSD1 tAH3 tAC6 tRDS1 tRDH1 tRSD1 tRSD2 tAH2 tAC4 tRDS2 tRDH2 tWRD2 tWRD1 tWDS3 tWSW2 tAH3 tWDH3 tDACD2 tEDACD2 Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) CS Rev. 3.00 Mar 17, 2006 page 883 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 T2 T1 T1 A23 to A6, A0 tAD A5 to A1 CS7 to CS0 AS tRSD2 RD Read D15 to D0 tAA1 tRDS2 tRDH2 HWR, LWR Figure 24.12 Burst ROM Access Timing: One-State Burst Access Rev. 3.00 Mar 17, 2006 page 884 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 T2 T3 T1 T2 A23 to A6, A0 tAD A5 to A1 CS7 to CS0 tAS1 AS tASD tASD tRSD2 RD Read D15 to D0 tAA3 tRDS2 tRDH2 tAH1 HWR, LWR Figure 24.13 Burst ROM Access Timing: Two-State Burst Access Rev. 3.00 Mar 17, 2006 page 885 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp tAD A23 to A0 tAS3 RAS5 to RAS2 tPCH2 UCAS Tr Tc1 Tc2 tAD tAH1 tCSD2 tAS2 tCASD1 tAH2 tCSD3 tCASD1 tCASW1 LCAS tOED1 OE, RD tAC1 tOED1 Read HWR tAC4 D15 to D0 tAA3 tRDS2 tRDH2 OE, RD tWRD2 Write HWR tWDD D15 to D0 tWCS1 tWCH1 tWRD2 tWDS1 tWDH2 AS tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 tEDACD2 tDACD2 Figure 24.14 DRAM Access Timing: Two-State Access Rev. 3.00 Mar 17, 2006 page 886 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS WAIT tWTS tWTH tWTS tWTH DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw : Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 24.15 DRAM Access Timing: Two-State Access, One Wait Rev. 3.00 Mar 17, 2006 page 887 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 A23 to A0 RAS5 to RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write HWR tRCH tRCS1 D15 to D0 AS tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tEDACD2 tDACD2 Notes: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 0 Figure 24.16 DRAM Access Timing: Two-State Burst Access Rev. 3.00 Mar 17, 2006 page 888 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp tAD A23 to A0 tAS2 RAS5 to RAS2 tPCH1 Tr Tc1 Tc2 Tc3 tAD tAH2 tCSD2 tAS3 tAH3 tCASD2 tCASW2 tCSD3 tCASD1 UCAS LCAS tOED2 OE, RD HWR tAC7 D15 to D0 tAC2 tOED1 Read tAA5 tRDS2 tRDH2 OE, RD HWR tWRD2 tWCS2 tWCH2 tWRD2 Write tWDD D15 to D0 tWDS2 tWDH3 AS DACK0, DACK1 tDACD1 tDACD2 tEDACD1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 1 tEDACD2 Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1) Rev. 3.00 Mar 17, 2006 page 889 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 Tc3 A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE Write HWR D15 to D0 tWTS tWTH WAIT tWTS tWTH DACK0, DACK1 EDACK0, EDACK1 Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw : Tcwp: Wait cycle inserted by programmable wait function Wait cycle inserted by pin wait function Figure 24.18 DRAM Access Timing: Three-State Access, One Wait Rev. 3.00 Mar 17, 2006 page 890 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 A23 to A0 RAS5 to RAS0 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write HWR tRCH tRCS2 D15 to D0 AS DACK0, DACK1 EDACK0 to EDACK3 Notes: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 1 Figure 24.19 DRAM Access Timing: Three-State Burst Access Rev. 3.00 Mar 17, 2006 page 891 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics TRp TRr TRc1 TRc2 tCSD1 RAS5 to RAS2 tCSD2 tCSR1 tCASD1 UCAS, LCAS tCASD1 OE Figure 24.20 CAS-Before-RAS Refresh Timing TRp tCSD1 RAS5 to RAS2 tCASD1 tCSD2 tCSR2 tCASD1 TRrw TRr TRc1 TRcw TRc2 UCAS, LCAS OE Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Rev. 3.00 Mar 17, 2006 page 892 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Self-refresh TRp tCSD2 RAS5 to RAS2 tCASD1 UCAS, LCAS tCASD1 tCSD2 TRr TRc TRc Tpsr DRAM access Tp Tr tRPS2 OE Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp tCSD2 RAS5 to RAS2 tCASD1 UCAS, LCAS tCSD2 tRPS1 tCASD1 TRr TRc TRc Tpsr DRAM access Tp Tr OE Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) Rev. 3.00 Mar 17, 2006 page 893 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics tBREQS BREQ tBACD BACK tBZD A23 to A0 tBZD tBACD tBREQS CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 24.24 External Bus Release Timing BACK tBRQOD BREQO tBRQOD Figure 24.25 External Bus Request Output Timing Rev. 3.00 Mar 17, 2006 page 894 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp Tr Tc1 Tw Tc2 SDRAM tAD2 Address bus Precharge-sel tCSD4 tCSD4 tCSD4 CAS WE CKE DQMU, DQML Data bus tCSD4 tCSD4 RAS tCSD4 Read tDQMD tDQMD High tRDS3 tRDH3 tCSD4 RAS tCSD4 tCSD4 CAS tCSD4 WE Write CKE High tDQMD DQMU, DQML tWDD Data bus tWDH4 tDQMD tCSD4 tCSD4 tCSD4 tCSD4 Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2) Note: Not supported in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 895 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics TRp TRr Software standby TRr2 SDRAM Address bus Precharge-sel RAS CAS WE tCKED CKE tCKED Figure 24.27 Synchronous DRAM Self-Refresh Timing Note: Not supported in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 896 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Tp Tr Tc1 Tc2 TRr Ttp2 SDRAM Address bus Precharge-sel RAS CAS WE tCKED tCKED CKE DQMU, DQML Data bus DACK or EDACK Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2) Note: Not supported in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 897 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics DMAC and EXDMAC Timing Table 24.9 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 EDREQ setup time EDREQ hold time ETEND delay time EDACK delay time 1 EDACK delay time 2 EDRAK delay time Symbol tDRQS tDRQH tTED tDACD1 tDACD2 tEDRQS tEDRQH tETED tEDACD1 tEDACD2 tEDRKD Min 25 10 -- -- -- 25 10 -- -- -- -- Max -- -- 18 18 18 -- -- 18 18 18 18 ns Figure 24.33 ns Figure 24.31 Figures 24.29, 24.30 ns Figure 24.32 ns Figure 24.31 Figures 24.29, 24.30 Unit ns Test Conditions Figure 24.32 Rev. 3.00 Mar 17, 2006 page 898 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 T2 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tEDACD2 tDACD2 Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access Rev. 3.00 Mar 17, 2006 page 899 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tEDACD1 EDACK0 to EDACK3 tEDACD2 tDACD2 Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Rev. 3.00 Mar 17, 2006 page 900 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 tTED TEND0, TEND1 tETED ETEND0 to ETEND3 T2 or T3 tTED tETED Figure 24.31 DMAC and EXDMAC TEND ETEND Output Timing TEND/ETEND tDRQS tDRQH DREQ0, DREQ1 tEDRQS tDERQH EDREQ0 to EDREQ3 Figure 24.32 DMAC and EXDMAC DREQ EDREQ Input Timing DREQ/EDREQ tEDRKD EDRAK0 to EDRAK3 tEDRKD Figure 24.33 EXDMAC EDRAK Output Timing Rev. 3.00 Mar 17, 2006 page 901 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Timing of On-Chip Peripheral Modules Table 24.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item I/O ports Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification WDT SCI Overflow output delay time Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tPWD tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD tScyc Min -- 25 25 -- -- 25 25 1.5 2.5 -- 25 25 1.5 2.5 -- 4 6 0.4 -- -- -- 40 40 30 Max 40 -- -- 40 40 -- -- -- -- 40 -- -- -- -- 40 -- -- 0.6 1.5 1.5 40 -- -- -- ns ns ns ns Figure 24.44 Figure 24.43 tScyc tcyc Unit ns ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc tcyc ns tcyc Figure 24.41 Figure 24.42 Figure 24.38 Figure 24.40 Figure 24.39 Figure 24.37 Figure 24.35 Figure 24.36 Test Conditions Figure 24.34 Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time Rev. 3.00 Mar 17, 2006 page 902 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics T1 tPRS tPRH Ports 1 to 8, A to H (read) T2 tPWD Ports 1 to 3, 6 to 9, P53 to P50, ports A to H (write) Figure 24.34 I/O Port Input/Output Timing tPOD PO15 to PO0 Figure 24.35 PPG Output Timing tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 24.36 TPU Input/Output Timing Rev. 3.00 Mar 17, 2006 page 903 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 24.37 TPU Clock Input Timing tTMOD TMO0, TMO1 Figure 24.38 8-Bit Timer Output Timing tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 24.39 8-Bit Timer Clock Input Timing tTMRS TMRI0, TMRI1 Figure 24.40 8-Bit Timer Reset Input Timing Rev. 3.00 Mar 17, 2006 page 904 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics tWOVD WDTOVF tWOVD Figure 24.41 WDT Output Timing tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf Figure 24.42 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 24.43 SCI Input/Output Timing: Synchronous Mode tTRGS ADTRG Figure 24.44 A/D Converter External Trigger Input Timing Rev. 3.00 Mar 17, 2006 page 905 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics 24.4 A/D Conversion Characteristics Table 24.11 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- 0.5 -- Max 10 8.1 20 5 7.5 7.5 7.5 -- 8.0 Unit Bit s pF k LSB LSB LSB LSB LSB 24.5 D/A Conversion Characteristics Table 24.12 D/A Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 33 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit Bit s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions Rev. 3.00 Mar 17, 2006 page 906 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics 24.6 Flash Memory Characteristics Table 24.13 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0C to 75C (program/erase operating temperature range: regular specifications), Ta = 0C to 85C (program/erase operating temperature range: wide-range specifications) Item Programming time*1 *2 *4 Erase time*1 *3 *6 Reprogramming count Data retention time*9 Programming Wait time after SWE bit setting*1 Wait time after PSU bit setting*1 Wait time after P bit setting*1 *4 Symbol Min tP tE NWEC tDRP x y z z1 z2 z3 -- -- Typ 10 50 Max 200 1000 Unit ms/ 128 bytes ms/ 128 bytes Times Years s s s s s 1n6 7 n 1000 Additional programming wait Test Conditions 100*7 10,000*8 -- 10 1 50 -- -- -- -- -- -- -- -- -- -- -- -- 30 200 10 Wait time after P bit clearing*1 Wait time after PSU bit clearing*1 Wait time after PV bit setting*1 5 5 4 2 2 100 -- 1 100 -- 10 10 20 2 4 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- 100 s s s s s Wait time after H'FF dummy write*1 Wait time after PV bit clearing*1 *1 Wait time after SWE bit clearing Erasing Maximum number of writes*1 *4 Wait time after SWE bit setting*1 Wait time after ESU bit setting*1 Wait time after E bit setting*1 *6 Wait time after E bit clearing*1 Wait time after ESU bit clearing*1 Wait time after EV bit setting*1 N x y z s 1000*5 Times s s s s s s s s s Times Erase time wait Wait time after H'FF dummy write*1 Wait time after EV bit clearing*1 *1 Wait time after SWE bit clearing Maximum number of erases*1 *6 N Rev. 3.00 Mar 17, 2006 page 907 of 926 REJ09B0283-0300 Section 24 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time tP (max) = wait time after P bit setting (z) i=1 N 5. The maximum number of writes (N) should be set as shown below according to the actual set value of (z) so as not to exceed the maximum programming time (tP(max)). The wait time after P bit setting (z) should be changed as follows according to the number of writes (n). Number of writes (n) 1n6 z = 30 s 7 n 1000 z = 200 s (Additional programming) Number of writes (n) 1n6 z = 10 s 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): tE(max) = Wait time after E bit setting (z) x maximum number of erases (N) 7. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 8. Reference value for 25C (as a guideline, rewriting should normally function up to this value). 9. Data retention characteristic when rewriting is performed within the specification range, including the minimum value. 24.7 Usage Note The F-ZTAT and masked ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the F-ZTAT version, the same evaluation testing should also be conducted for the masked ROM version when changing over to that version. Rev. 3.00 Mar 17, 2006 page 908 of 926 REJ09B0283-0300 Appendix Appendix A. I/O Port States in Each Pin State MCU Operating Mode*1 1 to 7 1 to 7 1 to 7 1 to 7 Hardware Standby Mode T T T T Program Execution State Sleep Mode I/O port I/O port I/O port [OE (CKE)*2 output] OE (CKE)*2 [Other than the above] I/O port Port Name Port 1 Port 2 P34 to P30 P35/OE/ CKE Reset T T T T Software Standby Mode Keep Keep Keep [OPE = 0, OE (CKE)*2 output] T [OPE = 1, OE (CKE)*2 output] H [Other than the above] Keep Bus Release State Keep Keep Keep [OE (CKE)*2 output] T [Other than the above] Keep P47/DA1 1 to 7 T T [DAOE1 = 1] Keep [DAOE1 = 0] T Keep Input port P46/DA0 1 to 7 T T [DAOE0 = 1] Keep [DAOE0 = 0] T Keep Input port P45 to P40 P57/DA3 1 to 7 1 to 7 T T T T T [DAOE3 = 1] Keep [DAOE3 = 0] T T Keep Input port Input port P56/DA2 1 to 7 T T [DAOE2 = 1] Keep [DAOE2 = 0] T Keep Input port Rev. 3.00 Mar 17, 2006 page 909 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode Input port I/O port I/O port I/O port I/O port A23 to A21 [Other than the above] I/O port Port Name P55, P54 P53 to P50 Port 6 Port 7 Port 8 PA7/A23 PA6/A22 PA5/A21 MCU Operating Mode*1 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 Reset T T T T T T Hardware Standby Mode T T T T T T Software Standby Mode T Keep Keep Keep Keep [OPE = 0, address output] T [OPE = 1, address output] Keep [Other than the above] Keep Bus Release State T Keep Keep Keep Keep T [Other than the above] Keep [Address output] [Address output] PA4/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 1, 2, 5, 6 L T [OPE = 0] T [OPE = 1] Keep T Address output A20 to A16 3, 4, 7 T T [OPE = 0, address output] T [OPE = 1, address output] Keep [Other than the above] Keep [Address output] [Address output] T [Other than the above] Keep A20 to A16 [Other than the above] I/O port Port B 1, 2, 5, 6 L T [OPE = 0] T [OPE = 1] Keep T Address output A15 to A8 Rev. 3.00 Mar 17, 2006 page 910 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode A15 to A8 [Other than the above] I/O port Port Name Port B MCU Operating Mode*1 3, 4 Reset T Hardware Standby Mode T Software Standby Mode [OPE = 0, address output] T [OPE = 1, address output] Keep [Other than the above] Keep Bus Release State T [Other than the above] Keep [Address output] [Address output] 3, 7 T T [OPE = 0, address output] T [OPE = 1, address output] Keep [Other than the above] Keep [Address output] [Address output] T [Other than the above] Keep A15 to A8 [Other than the above] I/O port Port C 1, 2, 5, 6 L T [OPE = 0] T [OPE = 1] Keep T Address output A7 to A0 4 T T [OPE = 0, address output] T [OPE = 1, address output] Keep [Other than the above] Keep [Address output] [Address output] T [Other than the above] Keep A7 to A0 [Other than the above] I/O port Rev. 3.00 Mar 17, 2006 page 911 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode A7 to A0 [Other than the above] I/O port Port Name Port C MCU Operating Mode*1 3, 7 Reset T Hardware Standby Mode T Software Standby Mode [OPE = 0, address output] T [OPE = 1, address output] Keep [Other than the above] Keep Bus Release State T [Other than the above] Keep [Address output] [Address output] Port D 1, 2, 4 to 6 3, 7 T T T T T [Data bus] T [Other than the above] Keep T [Data bus] T [Other than the above] Keep Keep T Keep [Data bus] T [Other than the above] Keep [Clock output] Clock output [Other than the above] Keep D15 toD8 [Data bus] D15 to D8 [Other than the above] I/O port I/O port D7 to D0 I/O port [Data bus] D7 to D0 [Other than the above] I/O port [Clock output] Clock output [Other than the above] Input port Port E 1, 2, 4 to 6 8-bit bus 16-bit bus T T T T T T T T Keep T Keep [Data bus] T [Other than the above] Keep 3, 7 8-bit bus 16-bit bus PF7/ 1, 2, 4 to 6 3, 7 Clock output T T [Clock output] H [Other than the above] Keep Rev. 3.00 Mar 17, 2006 page 912 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode [AS output] AS [Other than the above] I/O port Port Name PF6/AS MCU Operating Mode*1 1, 2, 4 to 6 Reset H Hardware Standby Mode T Software Standby Mode [OPE = 0, AS output] T [OPE = 1, AS output] H [Other than the above] Keep Bus Release State [AS output] T [Other than the above] Keep 3, 7 T PF5/RD PF4/HWR 1, 2, 4 to 6 H T [OPE = 0] T [OPE = 1] H T RD, HWR 3, 7 T [OPE = 0, RD, HWR output] T [OPE = 1, RD, HWR output] H [Other than the above] Keep [RD, HWR output] T [Other than the above] Keep [RD, HWR output] RD, HWR [Other than the above] I/O port PF3/LWR 1, 2, 4 to 6 H T [OPE = 0, LWR output] T [OPE = 1, LWR output] H [Other than the above] Keep [LWR output] T [Other than the above] Keep [LWR output] LWR [Other than the above] I/O port 3, 7 T Rev. 3.00 Mar 17, 2006 page 913 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode [LCAS (DQML) output] LCAS (DQML) [Other than the above] I/O port Port Name PF2/LCAS/ DQML*2 MCU Operating Mode*1 1 to 7 Reset T Hardware Standby Mode T Software Standby Mode [OPE = 0, LCAS (DQML) output] T [OPE = 1, LCAS (DQML) output] H [Other than the above] Keep Bus Release State [LCAS (DQML) output] T [Other than the above] Keep PF1/UCAS/ (DQMU)*2 1 to 7 T T [OPE = 0, UCAS (DQMU) output] T [OPE = 1, UCAS (DQMU) output] H [Other than the above] Keep [UCAS (DQMU) output] T [Other than the above] Keep [UCAS (DQMU) output] UCAS [Other than the above] I/O port PF0/WAIT 1 to 7 T T [WAIT input] T [Other than the above] Keep [WAIT input] T [Other than the above] Keep [BREQ input] BREQ [WAIT input] WAIT [Other than the above] I/O port [BREQ input] BREQ [Other than the above] I/O port PG6/BREQ 1 to 7 T T [BREQ input] T [Other than the above] Keep Rev. 3.00 Mar 17, 2006 page 914 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode [BACK output] BACK [Other than the above] I/O port [BREQO output] BREQO [Other than the above] Keep [CS output] T [Other than the above] Keep [BREQO output] BREQO [Other than the above] I/O port [CS output] CS [Other than the above] I/O port Port Name PG5/BACK MCU Operating Mode*1 1 to 7 Reset T Hardware Standby Mode T Software Standby Mode [BACK output] T [Other than the above] Keep Bus Release State BACK PG4/ BREQO 1 to 7 T T [BREQO output] T [Other than the above] Keep PG3/CS3 PG2/CS2 PG1/CS1 1 to 7 T T [OPE = 0, CS output] T [OPE = 1, CS output] H [Other than the above] Keep PG0/CS0 1, 2, 5, 6 3, 4, 7 H T T [OPE = 0, CS output] T [OPE = 1, CS output] H [Other than the above] Keep [CS output] T [Other than the above] Keep [CS output] CS [Other than the above] I/O port Rev. 3.00 Mar 17, 2006 page 915 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode [OE output] OE [CS output] CS [Other than the above] I/O port Port Name PH3/OE/ CKE/CS7 MCU Operating Mode*1 1 to 7 Reset T Hardware Standby Mode T Software Standby Mode [OPE = 0, OE output] T [OPE = 1, OE output] H [OPE = 0, CS output] T [OPE = 1, CS output] H [Other than the above] Keep Bus Release State [OE output] T [CS output] T [Other than the above] Keep PH2/CS6 1 to 7 T T [OPE = 0, CS output] T [OPE = 1, CS output] H [Other than the above] Keep [CS output] T [Other than the above] Keep [CS output] CS [Other than the above] I/O port PH1/CS5/ SDRAM*2 1 to 7 [DCTL = 1] Clock output [DCTL = 0] T [DCTL = 1] [DCTL = 1] L L [DCTL = 0] [DCTL = 0, OPE = 0, T CS output] T [DCTL = 0, OPE = 1, CS output] H [Other than the above] Keep [DCTL = 1] Clock output [DCTL = 0, CS output] T [Other than the above] Keep [DCTL = 1] Clock output [DCTL = 0, CS output] CS [Other than the above] I/O port Rev. 3.00 Mar 17, 2006 page 916 of 926 REJ09B0283-0300 Appendix Program Execution State Sleep Mode [CS output] CS [Other than the above] I/O port Port Name PH0/CS4 MCU Operating Mode*1 1 to 7 Reset T Hardware Standby Mode T Software Standby Mode [OPE = 0, CS output] T [OPE = 1, CS output] H [Other than the above] Keep Bus Release State [CS output] T [Other than the above] Keep Legend: L: Low level H: High level Keep: Input port becomes high-impedance, output port retains state T: High impedance DDR: Data direction register OPE: Output port enable Notes: 1. Mode 3 is not supported in the H8S/2678 Group. 2. Not available in the H8S/2678 Group. Rev. 3.00 Mar 17, 2006 page 917 of 926 REJ09B0283-0300 Appendix B. Product Product Lineup Type Name Flash memory version Masked ROM version HD64F2676 HD6432676 HD6432675 HD6412674R HD6432673 HD6412670 Model Marking HD64F2676 HD64F2676(***) HD6432675(***) HD6412674 HD6432673(***) HD6412670 Package (Code) 144-pin QFP (FP-144G) 144-pin QFP (FP-144G) 144-pin QFP (FP-144G) 144-pin LQFP (FP-144H) 144-pin QFP (FP-144G) 144-pin QFP (FP-144G) H8S/2676 H8S/2675 H8S/2674R H8S/2673 H8S/2670 Legend: Masked ROM version ROM-less version Masked ROM version ROM-less version (***): ROM code Rev. 3.00 Mar 17, 2006 page 918 of 926 REJ09B0283-0300 Appendix C. Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages have priority. JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KC-A Previous Code FP-144H/FP-144HV MASS[Typ.] 1.4g HD *1 D 108 109 73 72 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section 144 1 ZD Index mark A Reference Dimension in Millimeters Symbol 37 36 A2 F A1 L L1 e *3 y bp Detail F x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 20 20 1.45 21.7 22.0 22.3 21.7 22.0 22.3 1.70 0.04 0.12 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.08 0.10 1.25 1.25 0.4 0.5 0.6 1.0 Min ZE Figure C.1 Package Dimensions (FP-144H) Rev. 3.00 Mar 17, 2006 page 919 of 926 REJ09B0283-0300 c Appendix JEITA Package Code P-QFP144-20x20-0.50 RENESAS Code PRQP0144KA-A Previous Code FP-144G/FP-144GV MASS[Typ.] 2.4g HD *1 D 108 109 73 72 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E Terminal cross section ZE c Reference Dimension in Millimeters Symbol 144 1 ZD 36 37 F L L1 A1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 20 20 2.70 21.8 22.0 22.2 21.8 22.0 22.2 3.05 0.00 0.10 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.10 0.10 1.25 1.25 0.4 0.5 0.6 1.0 Min A A2 Figure C.2 Package Dimensions (FP-144G) Rev. 3.00 Mar 17, 2006 page 920 of 926 REJ09B0283-0300 c Index Index 16-Bit Timer Pulse Unit.......................... 521 Buffer Operation ................................. 566 Cascaded Operation ............................ 570 Free-running count operation.............. 560 Input Capture Function ....................... 563 periodic count operation ..................... 560 Phase Counting Mode......................... 577 PWM Modes....................................... 572 Synchronous Operation....................... 564 toggle output ....................................... 562 Waveform Output by Compare Match 561 8-Bit Timers............................................ 627 16-Bit Counter Mode .......................... 641 Compare Match Count Mode.............. 641 Operation with Cascaded Connection. 641 Pulse Output........................................ 636 TCNT Incrementation Timing ............ 637 Toggle output...................................... 646 A/D Converter ........................................ 741 Conversion Time................................. 753 DTC Activation................................... 585 External Trigger .................................. 756 Scan Mode .......................................... 752 Single Mode........................................ 752 Address Space........................................... 28 Addressing Modes .................................... 48 Absolute Address.................................. 50 Immediate ............................................. 51 Memory Indirect ................................... 51 Program-Counter Relative .................... 51 Register Direct ...................................... 49 Register Indirect.................................... 49 Register Indirect with Displacement..... 49 Register indirect with post-increment ... 50 Register indirect with pre-decrement .... 50 Bcc ......................................................37, 45 Bus Controller .........................................121 Auto Refreshing ..................................218 Basic Bus Interface .............................158 Basic Operation Timing ..............160, 202 Basic Timing .......................................229 Burst ROM Interface...........................229 Bus Arbitration....................................255 Bus Release .........................................250 Chip Select (CS) Assertion Period Extension States ..............................155 Data Size and Data Alignment ............158 DRAM Interface..................................173 Idle Cycle ............................................232 Read Strobe (RD) Timing ...................170 Self-Refreshing ...................................220 Synchronous DRAM Interface............198 Valid Strobes.......................................160 Wait Control........................................169 Write Data Buffer Function.................249 Clock Pulse Generator.............................811 PLL Circuit .........................................816 Condition Field .........................................47 Condition-Code Register (CCR) ...............32 CPU Operating Modes ..............................24 Advanced Mode ....................................26 Normal Mode ..................................24, 25 D/A Converter.........................................763 data direction register..............................427 data register .............................................427 Data Transfer Controller .........................401 Activation by Software ...............416, 420 Block Transfer Mode ..........................414 Chain Transfer.............................415, 422 Chain Transfer when Counter = 0 .......423 DTC Vector Table...............................408 Rev. 3.00 Mar 17, 2006 page 921 of 926 REJ09B0283-0300 Index Normal Mode.............................. 412, 421 Register Information ........................... 408 Repeat Mode....................................... 413 Software Activation ............................ 425 vector number for the software activation ........................................................ 406 DMA Controller...................................... 259 Activation by Auto-Request ............... 288 Activation by External Request .......... 287 Block Transfer Mode.................. 304, 313 Burst Mode ......................................... 312 Idle Mode............................................ 292 Interrupt Sources................................. 329 Multi-Channel Operation.................... 325 Normal Mode...................................... 301 Repeat Mode....................................... 295 Sequential Mode ................................. 290 Single Address Mode.................. 298, 318 Transfer Modes................................... 288 Write Data Buffer Function ........ 324, 331 Effective Address Extension..................... 47 Exception Handling ............................ 75, 76 Interrupts............................................... 80 Reset exception handling ...................... 77 Stack Status after Exception Handling.. 82 Traces ................................................... 80 Trap Instruction .................................... 81 Exception Vector Table ............................ 75 EXDMA Controller ................................ 335 Auto Request Mode ............................ 355 Block Transfer Mode.......................... 358 Burst Mode ......................................... 356 Cycle Steal Mode................................ 355 Dual Address Mode ............................ 351 External Request Mode....................... 355 Normal Transfer Mode ....................... 357 Single Address Mode.......................... 352 Extended Register (EXR) ......................... 31 Flash Memory ......................................... 773 Boot Mode .......................................... 789 Erase Block ......................................... 784 Erase/Erase-Verify .............................. 798 Error Protection................................... 800 Hardware Protection ........................... 800 Program/Program-Verify .................... 796 Programmer Mode .............................. 801 Programming is performed in 128-byte units................................................. 778 Software Protection............................. 800 General Registers ...................................... 30 input pull-up MOS .................................. 427 Instruction Set ........................................... 37 Arithmetic operations...................... 37, 40 Bit Manipulation Instructions ............... 43 Block Data Transfer Instructions .......... 47 Branch Instructions ............................... 45 Data Transfer Instructions..................... 39 Logic Operations Instructions ............... 42 Shift Instructions ................................... 42 System Control Instructions.................. 46 Interrupt Control Modes.......................... 107 Interrupt Controller ................................... 85 Interrupt Exception Handling Vector Table ............................................................ 102 Interrupt Mask Bit..................................... 32 interrupt mask level................................... 31 interrupt priority register (IPR) ................. 85 Interrupts ADI ..................................................... 756 CMIA .................................................. 642 CMIB .................................................. 642 EXDMTEND ...................................... 395 NMI..................................................... 118 NMI Interrupt...................................... 101 OVI ..................................................... 642 SWDTEND ......................................... 416 Rev. 3.00 Mar 17, 2006 page 922 of 926 REJ09B0283-0300 Index TCI1U................................................. 584 TCI1V................................................. 584 TCI2U................................................. 584 TCI2V................................................. 584 TCI3V................................................. 584 TCI4U................................................. 584 TCI4V................................................. 584 TCI5U................................................. 584 TCI5V................................................. 584 TGI0A................................................. 584 TGI0B ................................................. 584 TGI0C................................................. 584 TGI0D................................................. 584 TGI0V................................................. 584 TGI1A................................................. 584 TGI1B ................................................. 584 TGI2A................................................. 584 TGI2B ................................................. 584 TGI3A................................................. 584 TGI3B ................................................. 584 TGI3C................................................. 584 TGI3D................................................. 584 TGI4A................................................. 584 TGI4B ................................................. 584 TGI5A................................................. 584 TGI5B ................................................. 584 WOVI ................................................. 656 List of Registers ...................................... 833 Register Addresses.............................. 833 Register Bits........................................ 844 Register States in Each Operating Mode ........................................................ 856 MCU Operating Modes ............................ 57 Multiply-Accumulate Register (MAC) ..... 33 On-Board Programming.......................... 788 open-drain control register...................... 427 Operation Field ......................................... 47 port register .............................................427 Program Counter (PC) ..............................31 Programmable Pulse Generator...............605 Non-Overlapping Pulse Output ...........619 output trigger.......................................612 RAM .......................................................771 Register Field ............................................47 Registers ABWCR ...................... 126, 836, 848, 858 ADCR ......................... 750, 841, 852, 862 ADCSR ....................... 746, 841, 852, 862 ADDR ................. 744, 840, 841, 852, 862 ASTCR........................ 126, 836, 848, 858 BCR............................. 136, 837, 848, 859 BROMCR.................... 135, 837, 848, 859 BRR............. 679, 840, 851, 852, 861, 862 CRA ............................ 405, 834, 844, 856 CRB............................. 405, 834, 844, 856 CSACR................ 133, 837, 848, 858, 859 DACR ......................... 766, 841, 853, 862 DADR ......................... 765, 841, 853, 862 DAR ............................ 405, 834, 844, 856 DMABCR ................... 272, 838, 849, 859 DMACR ...................... 265, 838, 849, 859 DMATCR.................... 285, 838, 849, 859 DMAWER .................. 283, 837, 849, 859 DRACCR .................... 144, 837, 848, 859 DRAMCR ................... 138, 837, 848, 859 DTCER ....................... 405, 838, 850, 860 DTVECR..................... 406, 838, 850, 860 EBR1........................... 784, 842, 853, 863 EBR2........................... 785, 842, 853, 863 EDACR ............... 346, 834, 844, 845, 856 EDDAR............... 339, 834, 844, 845, 856 EDMDR ...................... 834, 844, 845, 856 EDSAR................ 338, 834, 844, 845, 856 EDTCR ............... 339, 834, 844, 845, 856 ETCR .......................... 264, 837, 849, 859 FLMCR1 ..................... 781, 842, 853, 863 Rev. 3.00 Mar 17, 2006 page 923 of 926 REJ09B0283-0300 Index FLMCR2..................... 783, 842, 853, 863 IER................................ 91, 838, 850, 860 INTCR .......................... 88, 838, 850, 860 IOAR .......................... 263, 837, 849, 859 IPR.................88, 834, 835, 845, 856, 857 IrCR ............................ 688, 835, 846, 857 ISCR ............................. 92, 835, 846, 857 ISR ................................ 98, 838, 850, 860 ITSR ............................. 98, 835, 846, 857 MAR ................... 263, 837, 848, 849, 859 MDCR .......................... 59, 838, 850, 860 MRA ........................... 403, 834, 844, 856 MRB ........................... 404, 834, 844, 856 MSTPCR .................... 824, 838, 850, 860 NDER ......................... 608, 838, 850, 860 NDR.................... 610, 838, 839, 850, 860 P1DDR........................ 432, 835, 846, 857 P1DR .......................... 433, 839, 851, 861 P2DDR........................ 443, 835, 846, 857 P2DR .......................... 444, 839, 851, 861 P3DDR........................ 454, 835, 846, 857 P3DR .......................... 455, 839, 851, 861 P3ODR........................ 456, 836, 846, 857 P5DDR........................ 463, 835, 846, 857 P5DR .......................... 463, 839, 851, 861 P6DDR........................ 467, 835, 846, 857 P6DR .......................... 468, 839, 851, 861 P7DDR........................ 472, 835, 846, 857 P7DR .......................... 473, 839, 851, 861 P8DDR........................ 478, 835, 846, 857 P8DR .......................... 479, 839, 851, 861 PADDR....................... 484, 835, 846, 857 PADR.......................... 485, 839, 851, 861 PAODR....................... 486, 836, 846, 857 PAPCR........................ 486, 835, 846, 857 PBDDR....................... 490, 835, 846, 857 PBDR.......................... 490, 839, 851, 861 PBPCR........................ 491, 835, 846, 857 PCDDR....................... 493, 835, 846, 857 PCDR.......................... 494, 839, 851, 861 Rev. 3.00 Mar 17, 2006 page 924 of 926 REJ09B0283-0300 PCPCR ........................ 495, 835, 846, 857 PCR............................. 612, 838, 850, 860 PDDDR ....................... 497, 835, 846, 857 PDDR.......................... 497, 839, 851, 861 PDPCR........................ 498, 835, 846, 857 PEDDR ....................... 500, 835, 846, 857 PEDR .......................... 501, 839, 851, 861 PEPCR ........................ 502, 835, 846, 857 PFCR0......................... 513, 835, 846, 857 PFCR1......................... 486, 835, 846, 857 PFCR2......................... 457, 835, 846, 857 PFDDR........................ 504, 835, 846, 857 PFDR .......................... 505, 839, 851, 861 PGDDR ....................... 510, 835, 846, 857 PGDR.......................... 512, 839, 851, 861 PHDDR ....................... 517, 840, 851, 861 PHDR.......................... 518, 839, 851, 861 PLLCR ........................ 813, 838, 850, 860 PMR ............................ 613, 838, 850, 860 PODR.......................... 609, 838, 850, 860 PORT1 ........................ 433, 839, 850, 860 PORT2 ........................ 444, 839, 850, 860 PORT3 ........................ 455, 839, 850, 860 PORT4 ........................ 461, 839, 850, 860 PORT5 ........................ 464, 839, 850, 860 PORT6 ........................ 468, 839, 851, 860 PORT7 ........................ 473, 839, 851, 861 PORT8 ........................ 479, 839, 851, 861 PORTA ....................... 485, 839, 851, 861 PORTB........................ 491, 839, 851, 861 PORTC........................ 494, 839, 851, 861 PORTD ....................... 498, 839, 851, 861 PORTE........................ 501, 839, 851, 861 PORTF ........................ 506, 839, 851, 861 PORTG ....................... 512, 839, 851, 861 PORTH ....................... 518, 839, 851, 861 RAMER ...................... 786, 837, 848, 859 RDNCR....................... 132, 837, 848, 858 RDR ............ 665, 840, 851, 852, 861, 862 REFCR........................ 149, 837, 848, 859 Index RSTCSR ..................... 653, 842, 853, 863 RTCNT ....................... 152, 837, 848, 859 RTCOR ....................... 152, 837, 848, 859 SAR............................. 405, 834, 844, 856 SBYCR ....................... 822, 838, 850, 860 SCKCR ....................... 812, 838, 850, 860 SCMR ......... 678, 840, 851, 852, 861, 862 SCR............. 670, 840, 851, 852, 861, 862 SEMR ......................... 689, 834, 844, 856 SMR............ 666, 840, 851, 852, 861, 862 SSIER ......................... 100, 835, 846, 857 SSR ............. 673, 840, 851, 852, 861, 862 SYSCR.......................... 59, 838, 850, 860 TCNT......... 557, 630, 651, 836, 843, 847, 853, 854, 858, 863 TCORA....................... 630, 842, 853, 863 TCORB ....................... 630, 842, 853, 863 TCR ........... 528, 631, 836, 842, 843, 847, 853, 854, 858, 862, 863 TCSR .......... 633, 651, 842, 853, 862, 863 TDR ............ 666, 840, 851, 852, 861, 862 TGR ........... 557, 836, 843, 847, 853, 854, 858, 863 TIER .......... 552, 836, 842, 843, 847, 853, 854, 858, 863 TIOR.......... 534, 836, 842, 843, 847, 853, 854, 858, 863 TMDR........ 533, 836, 842, 843, 847, 853, 854, 858, 863 TSR ............ 554, 666, 836, 842, 843, 847, 853, 854, 858, 863 TSTR........................... 557, 842, 853, 863 TSYR .......................... 558, 842, 853, 863 WTCR ................. 127, 836, 837, 848, 858 Reset..........................................................77 RRRDACR..............................................766 RRRDADR .............................................765 RRRMDCR...............................................59 RRRSYSCR ..............................................59 Serial Communication Interface..............661 Asynchronous Mode ...........................691 Bit Rate ...............................................679 Break ...................................................735 framing error .......................................698 Mark State ...........................................736 Operation in Clocked Synchronous Mode ........................................................709 overrun error .......................................698 parity error...........................................698 stack pointer (SP) ......................................30 Trace Bit....................................................31 TRAPA instruction ...................................51 Watchdog Timer .....................................649 Interval Timer Mode ...........................655 Watchdog Timer Mode .......................654 Rev. 3.00 Mar 17, 2006 page 925 of 926 REJ09B0283-0300 Index Rev. 3.00 Mar 17, 2006 page 926 of 926 REJ09B0283-0300 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTATTM Publication Date: 1st Edition, September 2001 Rev.3.00, March 17, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTATTM Hardware Manual |
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